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ds07-16401-3e fujitsu semiconductor data sheet 32-bit risc microcontroller cmos FR50 family mb91360g series mb91fv360ga/f362ga/f369ga n description the fujitsu mb91360g series is a standard microcontroller containing a wide range of i/o peripherals and bus control functions. the mb91360g series features a 32-bit risc cpu (FR50 series) core and is suitable for embedded control applications requiring high-performance and high-speed cpu processing. the mb91360g series also contains up to 4 kbytes instruction cache memory and other internal memories to improve the execution speed of the cpu. n features ? execution time : down to 15.6 ns ( 64 mhz ) ? FR50 series cpu : risc architecture the cpu has a general-purpose register architecture with improved numeric implementation whereby a wide range of delayed branch instructions reduces losses in execution time due to pipeline breaks. bit manipulation instructions and memory access instructions have been enhanced resulting in improved code efficiency and execution speed for control implementation. a five-stage pipeline structure provides high-speed processing (one instruction per cycle) 32-bit linear address space : 4 gbytes fixed 16-bit instruction size (basic instructions) high-speed multiplication/step division high-speed interrupt processing (6 cycles) general-purpose registers : 16 32 bits (continued) n pac k ag e 401-pin ceramics pga 208-pin plastic qfp 160-pin plastic qfp (pga-401c-a02) (fpt-208p-m04) (fpt-160p-m15)
mb91360g series 2 (continued) ? external bus interface unit with a wide range of functions divides the external memory space into a maximum of eight areas. chip select signal setting, data bus width selection (8, 16, 32-bit) , and area size can be specified for each area. address bus up to 32 bit wide programmable auto-wait function ? internal instruction cache the mb91360g series contains up to 4-kbyte instruction cache to improve the execution speed of external programs. two-way set associative caching ? dmac direct memory access (dma) can be used to perform various types of data transfer without going via the cpu. this improves system performance. eight channels (including up to 3 external channels) three transfer modes supported : single/block, burst, continuous transfer ? power consumption control mechanisms the mb91360g series contains a number of functions for controlling the operating clock to reduce power consumption. software control : sleep and stop/real time clock functions hardware control : hardware standby function gear (divider) function : the cpu and peripheral clock frequencies can be set independently. ? contains a range of peripheral functions uart, u-timer real time clock (with optional subclock operation and subclock calibration module) stepper motor control sound generator serial io (sio) , sio-prescaler power down reset alarm comparator io-timer i 2 c interface 10 bit d/a converter can interface 10-bit a/d converter 16-bit reload timer 16-bit pwm timer watchdog timer bit search module interrupt controller external interrupt inputs i/o port function ? interrupt levels 16 maskable interrupt levels ? other power supply voltage 5 v power supply used, the internal regulator creates internal supply of 3.3 v package : mb91fv360ga uses a pga401 package, mb91f362ga is delivered in a qfp208 package, and mb91f369ga in qfp160 package.
mb91360g series 3 n product lineup resource channels memory size mb91fv360ga mb91f362ga mb91f369ga cache/instruction ram 4 kb / 4 kb - / 4 kb - / 4 kb d-bus ram 16 kb 12 kb 16 kb f-bus ram 16 kb 4 kb 16 kb flash/rom 512 kb on f-bus 512 kb on f-bus 512 kb on f-bus boot rom 2 kb 2 kb 2 kb can 4 ch 3 ch 2 ch stepper motor control 4 ch 4 ch ? sound generator 1 ch 1 ch 1 ch ppg 8 ch 8 ch 4 ch input capture 4 ch 4 ch ? output compare 4 ch 4 ch ? free running timer 2 ch 2 ch ? d/a converter 2 ch 2 ch ? a/d converter 16 ch 16 ch 10 ch i 2 c 100 khz i 2 c 400 khz 1 ch 1 ch 1 ch alarm comparator 1 ch 1 ch 1 ch sio/sio prescaler 2 ch 2 ch 2 ch uart/u-timer 3 ch 3 ch 1 ch 16-bit reload timer 6 ch 6 ch 6 ch ext. interrupt 8 ch 8 ch 8 ch non maskable interrupt 1 ?? real time clock 1 1 1 32 khz subclock option for rtc yes no no subclock calibration yes no no led port 8 bit 8 bit ? power down reset 1 1 1 bit search module 1 1 1 watchdog timer 1 1 1 ext. address bus 32 bit 21 bit up to 24 bit ext. data bus 32 bit 32 bit 32 bit ext. dma 3 ch 1 ch 1 ch max operating frequency 64 mhz 64 mhz 64 mhz
mb91360g series 4 n pin assignments mb91fv360ga (bottom view) (pga-401c-a02) 24 23 25 26 27 28 29 30 31 32 33 70 69 71 72 73 74 75 76 77 78 79 80 120 119 121 122 123 124 125 126 127 128 129 130 131 175 174 176 177 178 179 180 181 182 183 184 185 186 187 231 230 232 233 234 235 236 237 238 239 240 241 242 243 244 284 173 285 286 287 288 289 290 291 292 293 294 295 296 297 188 229 118 334 335 336 337 338 339 340 341 342 343 344 345 346 245 132 172 68 22 117 228 333 67 171 282 379 21 116 227 332 66 170 281 378 20 115 226 331 65 169 280 377 19 114 225 330 64 168 279 376 18 113 224 329 63 167 278 375 17 112 223 328 62 166 277 374 16 111 222 327 61 165 276 373 15 110 221 326 60 164 275 372 14 109 220 325 59 163 274 371 13 108 219 324 58 162 273 370 12 107 218 323 57 161 272 369 368 367 366 365 364 363 362 361 360 359 358 320 319 318 317 316 315 314 313 312 311 310 257 144 201 268 267 266 265 264 263 262 261 260 259 258 212 211 210 209 208 207 206 205 204 203 202 155 154 153 152 151 150 149 148 147 146 145 101 100 99 98 97 96 95 94 93 52 51 50 49 48 47 46 45 7 6 5 4 3 2 1 309 200 92 106 217 322 321 160 271 270 269 216 215 214 213 159 158 157 156 105 104 103 102 56 55 54 53 11 10 9 8 283 380 381 382 383 384 385 386 387 388 389 390 391 298 189 81 347 246 133 34 392 299 190 82 348 247 134 35 393 300 191 83 349 248 135 36 394 301 192 84 350 249 136 37 395 302 193 85 351 250 137 38 396 303 194 86 352 251 138 39 397 304 195 87 353 252 139 40 398 305 196 88 354 253 140 41 399 306 197 89 355 254 141 42 400 307 198 90 356 255 142 43 401 308 199 91 357 256 143 44 index
mb91360g series 5 mb91f362ga (top view) (fpt-208p-m04) 156 157 uart pq [5:0] pp [5:0] po [7:0] pn [5:0] pm [3:0] p9 [7:0] p8 [7:0] p7 [4:6] p6 [4:0] p5 [7:0] p4 [7:0] p3 [7:0] p2 [7:0] p1 [7:0] p0 [7:0] ps [7:0] pr [7:0] pl [7:0] pk [7:0] pj [7:0] pi [6:0] ph [7:0] pb [2:0] pg [7:0] can ppg sio i 2 c xtal + pll ocu icu led dac adc dma adc 53 52 1 208 index smc 105 104 sin2 sot1 sin1 sot0 sin0 rx2 tx2 rx1 tx1 rx0 tx0 v ss v dd ocpa7 ocpa6 ocpa5 ocpa4 ocpa3 ocpa2 ocpa1 ocpa0 sck3 sot3 sin3 sck4 sin4 sot4 scl sda sga sgo vci cpo v ss x1a x0a x1 x0 v dd selclk monclk initx hstx md2 md1 md0 v ss out3 out2 out1 out0 in3 d24 d25 d26 d27 d28 d29 d30 d31 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 v dd v ss a16 a17 a18 a19 a20 cs4x cs5x cs6x rdy bgrntx brq rdx wr0x wr1x wr2x wr3x as ale clk ah/boot cs0x cs1x cs2x cs3x v dd v ss in2 in1 in0 int7 int6 int5 int4 int3 int2 int1 int0 v ss v dd led7 led6 led5 led4 led3 led2 led1 led0 ltestx cputestx testx atgx v dd v ss alarm da1 da0 av ss an7 an6 an5 an4 an3 an2 an1 an0 avrh av cc deop0 dack0 dreq0 an15 an14 an13 an12 an11 an10 an9 an8 sot2 v ss v cc 3c v dd hv ss pwm1p0 pwm1m0 pwm2p0 pwm2m0 hv dd pwm1p1 pwm1m1 pwm2p1 pwm2m1 hv ss pwm1p2 pwm1m2 pwm2p2 pwm2m2 hv dd pwm1p3 pwm1m3 pwm2p3 pwm2m3 hv ss v dd d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 v dd v ss d15 d16 d17 d18 d19 d20 d21 d22 d23 ext. interrupt ext. bus data ext. bus address chip select ext. bus control chip select mode sound gen.
mb91360g series 6 mb91f369ga (top view) (fpt-160p-m15) p0 [3:0] pq [1:0] pp [3:0] pb [2:0] p8 [7:0] p7 [6:4] pn [5:0] pk [7:0] pg [1:0] ph [7:0] ext.bus control osci. can sio mode adc ext. bus data vss vdd35 rdy wr0x wr1x wr2x wr3x vss vdd35 vss monclk vdd vss x1 x0 vdd ocpa3 ocpa2 ocpa1 ocpa0 vss vdd sot0 sin0 rx1 tx1 rx0 tx0 vss vcc3c vddi vddi vddi vddi vss sck3 sot3 sin3 sck4 sin4 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 vdd35 vss d16 d17 d18 d19 d20 d21 d22 d23 d24 d25 d26 d27 d28 d29 d30 d31 vdd35 vss a0 a1 a2 a3 120 117 119 116 118 115 112 113 114 111 99 104 106 101 100 102 103 105 107 108 109 110 95 90 91 92 93 94 96 97 98 a4 a5 a6 a7 a8 a9 a10 a11 vdd35 clk vss a12 a13 a14 a15 a16 a17 a18 a19 a20 vdd35 vss cs4x cs5x cs6x rdx bgrntx brq as ale ah cs0x cs1x cs2x cs3x dreq0 dacx0 deop vss vdd35 1 2 7 6 5 4 3 9 10 8 11 13 12 14 16 15 17 18 19 20 21 30 29 28 27 26 25 24 23 22 40 39 38 37 36 35 34 33 32 31 121 125 130 129 128 123 127 126 124 122 142 141 140 139 137 138 136 135 133 134 132 131 150 149 151 152 148 147 146 145 144 143 159 158 157 154 155 156 153 160 sot4 scl sda sga sgo int7 int6 int5 int4 int3 int2 int1 int0 vss vdd ltestx cputestx testx initx hstx md2 md1 md0 atgx vdd vss alarm an9 an8 an7 an6 an5 an4 an3 an2 an1 an0 avss avcc avrh 80 76 71 72 73 74 75 77 78 79 61 62 63 64 65 66 67 68 69 70 51 52 53 54 55 56 57 58 59 60 41 42 43 44 45 46 47 48 49 50 81 84 88 89 82 86 83 85 87 ppg uart i c 2 sound gen. ext.interrupt ext. bus address dma chip select chip select ext. bus control pm [3:0] p13
mb91360g series 7 n pin descriptions ? mb91fv360ga i/o pins and their functions (continued) pin no. pin name i/o general purpose io port circuit type function 1d18i/o ? q ext. bus data bit 18 2d11i/o ? q ext. bus data bit 11 3d2i/o ? q ext. bus data bit 2 4 not connected 5 hvss ?? ? ? 6hvdd5b ?? ? ? 7 pwm2m1 i/o pr7 m smc 1 8 pwm1m1 i/o pr5 k smc 1 9 pwm1p0 i/o pr0 k smc 0 10 vdd5r ?? ? ? 11 vdd5p ?? ? ? 12 sck4 i/o pn2 a sio clock 13 vdd5j ?? ? ? 14 exram i ? p trace control 15 twrx o ? x trace control 16 tad9 o ? xtrace address 17 tad5 o ? xtrace address 18 tad3 o ? xtrace address 19 tdt68 i/o ? wtrace data 20 tdt63 i/o ? wtrace data 21 tdt57 i/o ? wtrace data 22 tdt49 i/o ? wtrace data 23 tdt23 i/o ? wtrace data 24 tdt16 i/o ? wtrace data 25 tdt7 i/o ? wtrace data 26 tdt2 i/o ? wtrace data 27 icd0 i/o ? nice data 28 iclk i/o ? lice clock 29 x0 ?? h 4 mhz oscillator pin 30 intx i ? u initial pin 31 md1 i ? t mode pin 1 32 in3 i/o pl3 a icu input 3 33 int3 i/o pk3 a ext. interrupt 3
mb91360g series 8 (continued) pin no. pin name i/o general purpose io port circuit type function 34 an3 i/o ph3 b adc input 3 35 dack2 i/o pb6 a dma acknowledge 2 36 an13 i/o pg5 b adc input 13 37 an8 i/o pg0 b adc input 8 38 ale i/o p91 a ext. bus control 39 wr1x i/o p85 s ext. bus control 40 rdx i/o p83 s ext. bus control 41 cs7x i/o ? a chip select 7 (cans) 42 a26 i/o ? q ext. bus address bit 26 43 a20 i/o ? q ext. bus address bit 20 44 a12 i/o ? q ext. bus address bit 12 45 d21 i/o ? q ext. bus data bit 21 46 d16 i/o ? q ext. bus data bit 16 47 d13 i/o ? q ext. bus data bit 13 48 d7 i/o ? q ext. bus data bit 7 49 d3 i/o ? q ext. bus data bit 3 50 vss ?? ? ? 51 pwm2p2 i/o ps2 k smc 2 52 pwm2p1 i/o pr6 k smc 1 53 pwm1p1 i/o pr4 k smc 1 54 not connected 55 sin1 i/o pq2 a uart 1 input 56 tx3 i/o pp6 q can 3 tx 57 sot3 i/o pn4 a sio output 58 sot4 i/o pn0 a sio output 59 not connected 60 not connected 61 sgo i/o pm0 a sound generator sgo 62 toex o ? x trace control 63 tad8 o ? x trace address 64 tad2 o ? x trace address 65 tdt67 i/o ? wtrace data 66 tdt60 i/o ? wtrace data
mb91360g series 9 (continued) pin no. pin name i/o general purpose io port circuit type function 67 tdt54 i/o ? wtrace data 68 tdt48 i/o ? wtrace data 69 tdt26 i/o ? wtrace data 70 tdt21 i/o ? wtrace data 71 tdt18 i/o ? wtrace data 72 tdt12 i/o ? wtrace data 73 tdt8 i/o ? wtrace data 74 tdt3 i/o ? wtrace data 75 ics2 o ? gice status 76 vdd5f ?? ? ? 77 rstx i ? e reset pin 78 out2 i/o pl6 a ocu output 2 79 in0 i/o pl0 a icu input 0 80 int2 i/o pk2 a ext. interrupt 2 81 an6 i/o ph6 b adc input 6 82 an1 i/o ph1 b adc input 1 83 avcc ?? ? analog vcc 84 deop0 i/o pb2 a dma eop 0 85 an14 i/o pg6 b adc input 14 86 an9 i/o pg1 b adc input 9 87 as i/o p90 a ext. bus control 88 brq i/o p82 a ext. bus control 89 cs6x i/o p76 a chip select 6 90 a23 i/o ? q ext. bus address bit 23 91 a17 i/o ? q ext. bus address bit 17 92 a11 i/o ? q ext. bus address bit 11 93 d27 i/o ? q ext. bus data bit 27 94 d22 i/o ? q ext. bus data bit 22 95 d17 i/o ? q ext. bus data bit 17 96 d6 i/o ? q ext. bus data bit 16 97 vdd5s ?? ? ? 98 pwm1m3 i/o ps5 k smc 3 99 pwm2m3 i/o ps7 m smc 3 100 hvdd5a ?? ?
mb91360g series 10 (continued) pin no. pin name i/o general purpose io port circuit type function 101 pwm2p0 i/o pr2 k smc0 102 vcc3/c ?? c bypass capacitor pin 103 sot1 i/o pq3 a uart 1 output 104 sin0 i/o pq0 a uart 0 input 105 tx1 i/o pp2 q can 1 tx 106 ocpa2 i/o po2 a ppg output 107 sck3 i/o pn5 a sio clock 108 sin4 i/o pn1 a sio input 109 scl i/o pm3 y i 2 c scl 110 tclk i/o ? w trace control 111 tad12 o ? x trace address 112 tad15 o ? x trace address 113 tad1 o ? x trace address 114 tdt65 i/o ? wtrace data 115 tdt59 i/o ? wtrace data 116 tdt55 i/o ? wtrace data 117 tdt51 i/o ? wtrace data 118 tdt42 i/o ? wtrace data 119 tdt32 i/o ? wtrace data 120 tdt27 i/o ? wtrace data 121 tdt22 i/o ? wtrace data 122 tdt11 i/o ? wtrace data 123 tdt4 i/o ? wtrace data 124 icd3 i/o ? n ice data 125 tdt1 i/o ? wtrace data 126 selclk i ? f clock selection 127 nmix i ? e non maskable interrupt 128 out1 i/o pl5 a ocu output 1 129 in1 i/o pl1 a icu input 1 130 int5 i/o pk5 a ext. interrupt 5 131 led4 i/o pj4 j led port 4 132 alarm i ? d alarm comparator input 133 an7 i/o ph7 b adc input 7 134 an2 i/o ph2 b adc input 2
mb91360g series 11 (continued) pin no. pin name i/o general purpose io port circuit type function 135 dack0 i/o pb1 a dma acknowledge 0 136 an10 i/o pg2 b adc input 10 137 cs0x i/o p94 a chip select 0 138 cs3x i/o p97 a chip select 3 139 bgrntx i/o p81 a ext. bus control 140 cs4x i/o p74 a chip select 4 141 a22 i/o ? q ext. bus address bit 22 142 a18 i/o ? q ext. bus address bit 18 143 a14 i/o ? q ext. bus address bit 14 144 a5 i/o ? q ext. bus address bit 5 145 index ?? ? ? 146 d30 i/o ? q ext. bus data bit 30 147 d26 i/o ? q ext. bus data bit 26 148 d19 i/o ? q ext. bus data bit 19 149 d10 i/o ? q ext. bus data bit 10 150 d9 i/o ? q ext. bus data bit 9 151 d5 i/o ? q ext. bus data bit 5 152 pwm2m2 i/o ps3 m smc 2 153 pwm1p3 i/o ps4 k smc 3 154 pwm2m0 i/o pr3 m smc 0 155 vss ?? ? ? 156 sot2 i/o pq5 a uart 2 output 157 sot0 i/o pq1 a uart 0 output 158 vdd5o ?? ? ? 159 ocpa7 i/o po7 a ppg output 160 ocpa5 i/o po5 a ppg output 161 ocpa1 i/o po1 a ppg output 162 vdd5k ?? ? ? 163 x1a o ? i 32 khz oscillator pin 164 x0a i ? i 32 khz oscillator pin 165 sda i/o pm2 y i 2 c sda 166 tad10 o ? x trace address 167 tad11 o ? x trace address 168 tdt66 i/o ? wtrace data
mb91360g series 12 (continued) pin no. pin name i/o general purpose io port circuit type function 169 tdt61 i/o ? wtrace data 170 tdt58 i/o ? wtrace data 171 tdt52 i/o ? wtrace data 172 tdt45 i/o ? wtrace data 173 tdt39 i/o ? wtrace data 174 tdt35 i/o ? wtrace data 175 tdt31 i/o ? wtrace data 176 tdt24 i/o ? wtrace data 177 tdt15 i/o ? wtrace data 178 tdt14 i/o ? wtrace data 179 tdt10 i/o ? wtrace data 180 icd1 i/o ? n ice data 181 icd2 i/o ? nice data 182 hstx i ? e hardware standby 183 out3 i/o pl7 a ocu output 3 184 out0 i/o pl4 a ocu output 0 185 int6 i/o pk6 a ext. interrupt 6 186 led7 i/o pj7 j led port 7 187 led1 i/o pj1 j led port 1 188 cputestx i ? etest input 189 da1 o ? c dac output 190 an4 i/o ph4 b adc input 4 191 deop1 i/o pb5 a dma eop 1 192 dack1 i/o pb4 a dma acknowledge 1 193 dreq0 i/o pb0 a dma request 0 194 clk i/o p92 a ext. bus clock 195 ah/boot i/o p93 a ext. bus control/boot signal 196 cs5x i/o p75 a chip select 5 197 a24 i/o ? q ext. bus address bit 24 198 a21 i/o ? q ext. bus address bit 21 199 a15 i/o ? q ext. bus address bit 15 200 a8 i/o ? q ext. bus address bit 8 201 a2 i/o ? q ext. bus address bit 2 202 a0 i/o ? q ext. bus address bit 0
mb91360g series 13 (continued) pin no. pin name i/o general purpose io port circuit type function 203 d29 i/o ? q ext. bus address bit 29 204 d25 i/o ? q ext. bus address bit 25 205 d20 i/o ? q ext. bus address bit 20 206 d15 i/o ? q ext. bus address bit 15 207 d4 i/o ? q ext. bus address bit 4 208 hvdd5c ?? ? ? 209 pwm1m2 i/o ps1 k smc2 210 pwm1p2 i/o ps0 k smc2 211 pwm1m0 i/o pr1 k smc0 212 sin2 i/o pq4 a uart 2 input 213 rx3 i/o pp7 q can 3 rx 214 vss ?? ? ? 215 rx0 i/o pp1 q can 0 rx 216 vdd5n ?? ? ? 217 ocpa4 i/o po4 a ppg output 218 ocpa0 i/o po0 a ppg output 219 sin3 i/o pn3 a sio input 220 vss ?? ? ? 221 sga i/o pm1 a sound generator sga 222 tad13 o ? x trace address 223 tad7 o ? x trace address 224 tad6 o ? x trace address 225 tdt64 i/o ? wtrace data 226 tdt56 i/o ? wtrace data 227 tdt50 i/o ? wtrace data 228 tdt44 i/o ? wtrace data 229 tdt41 i/o ? wtrace data 230 tdt37 i/o ? wtrace data 231 tdt34 i/o ? wtrace data 232 tdt30 i/o ? wtrace data 233 tdt25 i/o ? wtrace data 234 tdt20 i/o ? wtrace data 235 tdt9 i/o ? wtrace data 236 break i ? o ice break
mb91360g series 14 (continued) pin no. pin name i/o general purpose io port circuit type function 237 ics1 o ? gice status 238 ics0 o ? gice status 239 md2 i ? t mode pin 2 240 in2 i/o pl2 a icu input 2 241 int4 i/o pk4 a ext. interrupt 4 242 led6 i/o pj6 j led port 6 243 led3 i/o pj3 j led port 3 244 not connected 245 testx i ? etest input 246 da0 o ? c dac output 247 an5 i/o ph5 b adc input 5 248 an0 i/o ph0 b adc input 0 249 an15 i/o pg7 b adc input 15 250 cs1x i/o p95 a chip select 1 251 wr3x i/o p87 s ext. bus control 252 wr2x i/o p86 s ext. bus control 253 dreq2 i/o p73 a dma request 2 254 a19 i/o ? q ext. bus address bit 19 255 a13 i/o ? q ext. bus address bit 13 256 a7 i/o ? q ext. bus address bit 7 257 a4 i/o ? q ext. bus address bit 4 258 d31 i/o ? q ext. bus data bit 31 259 d28 i/o ? q ext. bus data bit 28 260 d23 i/o ? q ext. bus data bit 23 261 d14 i/o ? q ext. bus data bit 14 262 d8 i/o ? q ext. bus data bit 8 263 d1 i/o ? q ext. bus data bit 1 264 d0 i/o ? q ext. bus data bit 0 265 not connected 266 hvss ?? ? ? 267 not connected 268 vss ?? ? ? 269 rx2 i/o pp5 q can 2 rx 270 rx1 i/o pp3 q can 1 rx
mb91360g series 15 (continued) pin no. pin name i/o general purpose io port circuit type function 271 vss ?? ? ? 272 ocpa3 i/o po3 a ppg output 273 vss ?? ? ? 274 not connected 275 vdd5i ?? ? ? 276 tadscx o ? x trace control 277 tce1x o ? x trace control 278 tad4 o ? x trace address 279 tad0 o ? x trace address 280 tdt62 i/o ? wtrace data 281 tdt53 i/o ? wtrace data 282 tdt47 i/o ? wtrace data 283 tdt43 i/o ? wtrace data 284 tdt36 i/o ? wtrace data 285 tdt33 i/o ? wtrace data 286 tdt28 i/o ? wtrace data 287 tdt19 i/o ? wtrace data 288 tdt13 i/o ? wtrace data 289 tdt6 i/o ? wtrace data 290 tdt5 i/o ? wtrace data 291 x1 ?? h 4 mhz oscillator pin 292 monclk o ? g clock output for test purposes 293 md0 i ? t mode pin 0 294 int7 i/o pk7 a ext. interrupt 7 295 int1 i/o pk1 a ext. interrupt 1 296 led5 i/o pj5 j led port 5 297 ltestx i ? e test input 298 atgx i/o pi3 a analog reference low 299 avrl ?? r analog reference high 300 avrh ?? r dma request 1 301 dreq1 i/o pb3 a adc input 12 302 an12 i/o pg4 b adc input 11 303 an11 i/o pg3 b ext. bus control 304 wr0x i/o p84 s ext. bus control
mb91360g series 16 (continued) pin no. pin name i/o general purpose io port circuit type function 305 rdy i/o ? s ext. bus control 306 a25 i/o ? q ext. bus address bit 25 307 a16 i/o ? q ext. bus address bit 16 308 a10 i/o ? q ext. bus address bit 10 309 a6 i/o ? q ext. bus address bit 6 310 a1 i/o ? q ext. bus address bit 1 311 not connected 312 d24 i/o ? q ext. bus data bit 24 313 d12 i/o ? q ext. bus data bit 12 314 not connected 315 pwm2p3 i/o ps6 k smc 3 316 hvss ?? ? ? 317 hvss ?? ? ? 318 not connected 319 vdd5q ?? ? ? 320 tx2 i/o pp4 q can 2 tx 321 tx0 i/o pp0 q can 0 tx 322 ocpa6 i/o po6 a ppg output 323 vdd5m ?? ? ? 324 vdd5l ?? ? ? 325 not connected 326 vdd5h ?? ? ? 327 tad14 o ? x trace address 328 vss3 ?? ? ? 329 vss3 ?? ? ? 330 not connected 331 vdd3c ?? ? ? 332 tdt46 i/o ? wtrace data 333 tdt40 i/o ? wtrace data 334 tdt38 i/o ? wtrace data 335 vdd3b ?? ? ? 336 tdt29 i/o ? wtrace data 337 tdt17 i/o ? wtrace data 338 vdd3a ?? ? ?
mb91360g series 17 (continued) pin no. pin name i/o general purpose io port circuit type function 339 tdt0 i/o ? wtrace data 340 vss ?? ? ? 341 vss ?? ? ? 342 not connected 343 vdd5e ?? ? ? 344 int0 i/o pk0 a ext. interrupt 0 345 led2 i/o pj2 j led port 2 346 led0 i/o pj0 j led port 0 347 vdd5d ?? ? ? 348 avss ?? ? analog vss 349 deop2 i/o pb7 a dma eop 2 350 vdd5c ?? ? ? 351 cs2x i/o p96 a chip select 2 352 vss ?? ? ? 353 vss ?? ? ? 354 vdd5b ?? ? ? 355 not connected 356 a9 i/o ? q ext. bus address bit 9 357 a3 i/o ? q ext. bus address bit 3 358 vss ?? ? ? 359 vss ?? ? ? 360 vdd5t ?? ? ? 361 vss ?? ? ? 362 vss ?? ? ? 363 vss ?? ? ? 364 not connected 365 hvss ?? ? ? 366 vss ?? ? ? 367 vss ?? ? ? 368 not connected 369 vss ?? ? ? 370 vss ?? ? ? 371 not connected 372 vss ?? ? ?
mb91360g series 18 (continued) pin no. pin name i/o general purpose io port circuit type function 373 vss ?? ? ? 374 vss ?? ? ? 375 vdd3d ?? ? ? 376 vss3 ?? ? ? 377 vss3 ?? ? ? 378 vss3 ?? ? ? 379 not connected 380 vss3 ?? ? ? 381 vss3 ?? ? ? 382 not connected 383 vss3 ?? ? ? 384 vss3 ?? ? ? 385 vss3 ?? ? ? 386 vdd5g ?? ? ? 387 vss ?? ? ? 388 vss ?? ? ? 389 vss ?? ? ? 390 not connected 391 vss ?? ? ? 392 vss ?? ? ? 393 not connected 394 vss ?? ? ? 395 vss ?? ? ? 396 vss ?? ? ? 397 not connected 398 vss ?? ? ? 399 vss ?? ? ? 400 vss ?? ? ? 401 vdd5a ?? ? ?
mb91360g series 19 ? mb91fv362ga i/o pins and their functions (continued) pin no. pin name i/o general purpose io port circuit type function 1d24i/o ? q ext. bus data bit 24 2d25i/o ? q ext. bus data bit 25 3d26i/o ? q ext. bus data bit 26 4d27i/o ? q ext. bus data bit 27 5d28i/o ? q ext. bus data bit 28 6d29i/o ? q ext. bus data bit 29 7d30i/o ? q ext. bus data bit 30 8d31i/o ? q ext. bus data bit 31 9a0i/o ? q ext. bus address bit 0 10 a1 i/o ? q ext. bus address bit 1 11 a2 i/o ? q ext. bus address bit 2 12 a3 i/o ? q ext. bus address bit 3 13 a4 i/o ? q ext. bus address bit 4 14 a5 i/o ? q ext. bus address bit 5 15 a6 i/o ? q ext. bus address bit 6 16 a7 i/o ? q ext. bus address bit 7 17 a8 i/o ? q ext. bus address bit 8 18 a9 i/o ? q ext. bus address bit 9 19 a10 i/o ? q ext. bus address bit 10 20 a11 i/o ? q ext. bus address bit 11 21 a12 i/o ? q ext. bus address bit 12 22 a13 i/o ? q ext. bus address bit 13 23 a14 i/o ? q ext. bus address bit 14 24 a15 i/o ? q ext. bus address bit 15 25 vdd35 ?? ? separated ext. bus vdd, 3.3 v or 5.0 v 26 vss ?? ? ? 27 a16 i/o ? q ext. bus address bit 16 28 a17 i/o ? q ext. bus address bit 17 29 a18 i/o ? q ext. bus address bit 18 30 a19 i/o ? q ext. bus address bit 19 31 a20 i/o ? q ext. bus address bit 20 32 cs4x i/o p74 a chip select 4 33 cs5x i/o p75 a chip select 5
mb91360g series 20 (continued) pin no. pin name i/o general purpose io port circuit type function 34 cs6x i/o p76 a chip select 6 35 rdy i/o ? s ext. bus control 36 bgrnt i/o p81 a ext. bus control 37 brq i/o p82 a ext. bus control 38 rdx i/o ? s ext. bus control 39 wr0x i/o ? s ext. bus control 40 wr1x i/o ? s ext. bus control 41 wr2x i/o ? s ext. bus control 42 wr3x i/o ? s ext. bus control 43 as i/o p90 a ext. bus control 44 ale i/o p91 a ext. bus control 45 clk i/o ? a ext. bus clock 46 ah i/o p93 a ext. bus control signal 47 cs0x i/o p94 a chip select 0 48 cs1x i/o p95 a chip select 1 49 cs2x i/o p96 a chip select 2 50 cs3x i/o p97 a chip select 3 51 vdd35 ?? ? separated ext. bus vdd, 3.3 or 5.0 v 52 vss ?? ? ? 53 an8 i/o pg0 b adc input 8 54 an9 i/o pg1 b adc input 9 55 an10 i/o pg2 b adc input 10 56 an11 i/o pg3 b adc input 11 57 an12 i/o pg4 b adc input 12 58 an13 i/o pg5 b adc input 13 59 an14 i/o pg6 b adc input 14 60 an15 i/o pg7 b adc input 15 61 dreq0 i/o pb0 a dmr request 0 62 dack0 i/o pb1 a dma acknowledge 0 63 deop0 i/o pb2 a dma eop 0 64 avcc ?? ? analog vcc 65 avrh ?? r analog reference high 66 an0 i/o ph0 b adc input 0
mb91360g series 21 (continued) pin no. pin name i/o general purpose io port circuit type function 67 an1 i/o ph1 b adc input 1 68 an2 i/o ph2 b adc input 2 69 an3 i/o ph3 b adc input 3 70 an4 i/o ph4 b adc input 4 71 an5 i/o ph5 b adc input 5 72 an6 i/o ph6 b adc input 6 73 an7 i/o ph7 b adc input 7 74 avss, avrl ?? ? analog vss, analog reference low 75 da0 o ? c dac output 76 da1 o ? c dac output 77 alarm i ? d alarm comparator input 78 vss ?? ? ? 79 vdd ?? ? ? 80 atgx i/o pi3 a adc trigger input 81 testx i ? e test input (should be connected to vdd) 82 cputestx i ? e test input (should be connected to vdd) 83 ltestx i ? e test input (should be connected to vdd) 84 led0 i/o pj0 j led port 0 85 led1 i/o pj1 j led port 1 86 led2 i/o pj2 j led port 2 87 led3 i/o pj3 j led port 3 88 led4 i/o pj4 j led port 4 89 led5 i/o pj5 j led port 5 90 led6 i/o pj6 j led port 6 91 led7 i/o pj7 j led port 7 92 vdd ?? ? ? 93 vss ?? ? ? 94 int0 i/o pk0 a ext. interrupt 0 95 int1 i/o pk1 a ext. interrupt 1 96 int2 i/o pk2 a ext. interrupt 2 97 int3 i/o pk3 a ext. interrupt 3 98 int4 i/o pk4 a ext. interrupt 4 99 int5 i/o pk5 a ext. interrupt 5 100 int6 i/o pk6 a ext. interrupt 6
mb91360g series 22 (continued) pin no. pin name i/o general purpose io port circuit type function 101 int7 i/o pk7 a ext. interrupt 7 102 in0 i/o pl0 a icu input 0 103 in1 i/o pl1 a icu input 1 104 in2 i/o pl2 a icu input 2 105 in3 i/o pl3 a icu input 3 106 out0 i/o pl4 a ocu output 0 107 out1 i/o pl5 a ocu output 1 108 out2 i/o pl6 a ocu output 2 109 out3 i/o pl7 a ocu output 3 110 vss ?? ? ? 111 md0 i ? t mode pin 0 112 md1 i ? t mode pin 1 113 md2 i ? t mode pin 2 114 hstx i ? e hardware standby 115 initx i ? u initial pin 116 monclk o ? g system clock output for evaluation purposes 117 selclk i ? f clock selection, must be connected to vdd 118 vdd ?? ? ? 119 x0 ?? h 4 mhz oscillator pin 120 x1 ?? h 4 mhz oscillator pin 121 x0a i ? i reserved-must be connected to vss 122 x1a o ? i reserved-should be left open 123 vss ?? ? ? 124 cpo ?? c reserved-should be left open 125 vci ?? d reserved-must be connected to vss 126 sgo i/o pm0 a sound generator sgo 127 sga i/o pm1 a sound generator sga 128 sda i/o pm2 y i 2 c sda 129 scl i/o pm3 y i 2 c scl 130 sot4 i/o pn0 a sio output 131 sin4 i/o pn1 a sio input 132 sck4 i/o pn2 a sio clock 133 sin3 i/o pn3 a sio input 134 sot3 i/o pn4 a sio output
mb91360g series 23 (continued) pin no. pin name i/o general purpose io port circuit type function 135 sck3 i/o pn5 a sio clock 136 ocpa 0 i/o po0 a ppg output 137 ocpa 1 i/o po1 a ppg output 138 ocpa 2 i/o po2 a ppg output 139 ocpa 3 i/o po3 a ppg output 140 ocpa 4 i/o po4 a ppg output 141 ocpa 5 i/o po5 a ppg output 142 ocpa 6 i/o po6 a ppg output 143 ocpa 7 i/o po7 a ppg output 144 vdd ?? ? ? 145 vss ?? ? ? 146 tx0 i/o pp0 q can 0 tx 147 rx0 i/o pp1 q can 0 rx 148 tx1 i/o pp2 q can 1 tx 149 rx1 i/o pp3 q can 1 rx 150 tx2 i/o pp4 q can 2 tx 151 rx2 i/o pp5 q can 2 rx 152 sin0 i/o pq0 a uart 0 input 153 sot0 i/o pq1 a uart 0 output 154 sin1 i/o pq2 a uart 1 input 155 sot1 i/o pq3 a uart 1 output 156 sin2 i/o pq4 a uart 2 input 157 sot2 i/o pq5 a uart 2 output 158 vss ?? ? ? 159 vcc3/c ?? c bypass capacitor pin 160 vdd ?? ? ? 161 hvss ?? ? ? 162 pwm1p0 i/o pr0 k smc 0 163 pwm1m0 i/o pr1 k smc 0 164 pwm2p0 i/o pr2 k smc 0 165 pwm2m0 i/o pr3 m smc 0 166 hvdd ?? ? ? 167 pwm1p1 i/o pr4 k smc 1 168 pwm1m1 i/o pr5 k smc 1
mb91360g series 24 (continued) pin no. pin name i/o general purpose io port circuit type function 169 pwm2p1 i/o pr6 k smc 1 170 pwm2m1 i/o pr7 m smc 1 171 hvss ?? ? ? 172 pwm1p2 i/o ps0 k smc 2 173 pwm1m2 i/o ps1 k smc 2 174 pwm2p2 i/o ps2 k smc 2 175 pwm2m2 i/o ps3 m smc 2 176 hvdd ?? ? ? 177 pwm1p3 i/o ps4 k smc 3 178 pwm1m3 i/o ps5 k smc 3 179 pwm2p3 i/o ps6 k smc 3 180 pwm2m3 i/o ps7 m smc 3 181 hvss ?? ? ? 182 vdd35 ?? ? separated ext. bus vdd, 3.3 or 5.0 v 183 d0 i/o ? q ext. bus data bit 0 184 d1 i/o ? q ext. bus data bit 1 185 d2 i/o ? q ext. bus data bit 2 186 d3 i/o ? q ext. bus data bit 3 187 d4 i/o ? q ext. bus data bit 4 188 d5 i/o ? q ext. bus data bit 5 189 d6 i/o ? q ext. bus data bit 6 190 d7 i/o ? q ext. bus data bit 7 191 d8 i/o ? q ext. bus data bit 8 192 d9 i/o ? q ext. bus data bit 9 193 d10 i/o ? q ext. bus data bit 10 194 d11 i/o ? q ext. bus data bit 11 195 d12 i/o ? q ext. bus data bit 12 196 d13 i/o ? q ext. bus data bit 13 197 d14 i/o ? q ext. bus data bit 14 198 vdd35 ?? ? separated ext. bus vdd, 3.3 or 5.0 v 199 vss ?? ? ? 200 d15 i/o ? q ext. bus data bit 15 201 d16 i/o ? q ext. bus data bit 16 202 d17 i/o ? q ext. bus data bit 17
mb91360g series 25 (continued) note : if pins vdd35 (25, 51, 182, 198) are connected to 3.3 v then the external bus interface (pins 1-52, 182-208) can be operated at 3.3 v levels. pin no. pin name i/o general purpose io port circuit type function 203 d18 i/o ? q ext. bus data bit 18 204 d19 i/o ? q ext. bus data bit 19 205 d20 i/o ? q ext. bus data bit 20 206 d21 i/o ? q ext. bus data bit 21 207 d22 i/o ? q ext. bus data bit 22 208 d23 i/o ? q ext. bus data bit 23
mb91360g series 26 ? mb91f369ga i/o pins and their functions (continued) pin no. pin name i/o general purpose io port circuit type function 1a4i/o ? q ext. bus address bit 4 2a5i/o ? q ext. bus address bit 5 3a6i/o ? q ext. bus address bit 6 4a7i/o ? q ext. bus address bit 7 5a8i/o ? q ext. bus address bit 8 6a9i/o ? q ext. bus address bit 9 7a10i/o ? q ext. bus address bit 10 8a11i/o ? q ext. bus address bit 11 9vdd35 ?? ? separated ext. bus vdd, 3.3 or 5.0 v 10 clk i/o ? a ext. bus clock 11 vss ?? ? ? 12 a12 i/o ? q ext. bus address bit 12 13 a13 i/o ? q ext. bus address bit 13 14 a14 i/o ? q ext. bus address bit 14 15 a15 i/o ? q ext. bus address bit 15 16 a16 i/o ? q ext. bus address bit 16 17 a17 i/o ? q ext. bus address bit 17 18 a18 i/o ? q ext. bus address bit 18 19 a19 i/o ? q ext. bus address bit 19 20 a20 i/o ? q ext. bus address bit 20 21 vdd35 ?? ? separated ext. bus vdd, 3.3 or 5.0 v 22 vss ?? ? ? 23 cs4x i/o p74 a chip select 4 24 cs5x i/o p75 a chip select 5 25 cs6x i/o p76 a chip select 6 26 rdx i/o ? s ext. bus control 27 bgrntx i/o p81 a ext. bus control 28 brq i/o p82 a ext. bus control 29 as i/o p90 a ext. bus control 30 ale i/o p91 a ext. bus control 31 ah i/o p93 a ext. bus control signal 32 cs0x i/o p94 a chip select 0 33 cs1x i/o p95 a chip select 1
mb91360g series 27 (continued) pin no. pin name i/o general purpose io port circuit type function 34 cs2x i/o p96 a chip select 2 35 cs3x i/o p97 a chip select 3 36 dreq0 i/o pb0 a dma request 0 37 dack0 i/o pb1 a dma acknowledge 0 38 deop0 i/o pb2 a dma eop 0 39 vss ?? ? ? 40 vdd35 ?? ? separated ext. bus vdd, 3.3 or 5.0 v 41 avrh ?? r analog reference high 42 avcc ?? ? analog vcc 43 avss, avrl ?? ? analog vss, analog reference low 44 an0 i/o ph0 b adc input 0 45 an1 i/o ph1 b adc input 1 46 an2 i/o ph2 b adc input 2 47 an3 i/o ph3 b adc input 3 48 an4 i/o ph4 b adc input 4 49 an5 i/o ph5 b adc input 5 50 an6 i/o ph6 b adc input 6 51 an7 i/o ph7 b adc input 7 52 an8 i/o pg0 b adc input 8 53 an9 i/o pg1 b adc input 9 54 alarm i ? d alarm comparator input 55 vss ?? ? ? 56 vdd ?? ? ? 57 atgx i/o p13 a adc trigger input 58 md0 i ? t mode pin 0 59 md1 i ? t mode pin 1 60 md2 i ? t mode pin 2 61 hstx i ? e hardware standby 62 initx i ? u initual pin 63 testx i ? e test input (should be connected to vdd) 64 cputestx i ? e test input (should be connected to vdd) 65 ltestx i ? e test input (should be connected to vdd) 66 vdd ?? ? ?
mb91360g series 28 (continued) pin no. pin name i/o general purpose io port circuit type function 67 vss ?? ? ? 68 int0 i/o pk0 a ext. interrupt 0 69 int1 i/o pk1 a ext. interrupt 1 70 int2 i/o pk2 a ext. interrupt 2 71 int3 i/o pk3 a ext. interrupt 3 72 int4 i/o pk4 a ext. interrupt 4 73 int5 i/o pk5 a ext. interrupt 5 74 int6 i/o pk6 a ext. interrupt 6 75 int7 i/o pk7 a ext. interrupt 7 76 sgo i/o pm0 a sound generator sgo 77 sga i/o pm1 a sound generator sga 78 sda i/o pm2 y i 2 c sda 79 scl i/o pm3 y i 2 c scl 80 sot4 i/o pn0 a sio output 81 sin4 i/o pn1 a sio input 82 sck4 i/o pn2 a sio clock 83 sin3 i/o pn3 a sio input 84 sot3 i/o pn4 a sio output 85 sck3 i/o pn5 a sio clock 86 vss ?? ? ? 87 vddi ?? ? supply voltage for internal regulator 88 vddi ?? ? supply voltage for internal regulator 89 vddi ?? ? supply voltage for internal regulator 90 vddi ?? ? supply voltage for internal regulator 91 vcc3c ?? ? capacitor pin for internal regulator 92 vss ?? ? ? 93 tx0 i/o pp0 q can 0 tx 94 rx0 i/o pp1 q can 0 rx 95 tx1 i/o pp2 q can 1 tx 96 rx1 i/o pp3 q can 1 rx 97 sin0 i/o pq0 a uart 0 input 98 sot0 i/o pq1 a uart 0 output 99 vdd ?? ? ? 100 vss ?? ? ?
mb91360g series 29 (continued) pin no. pin name i/o general purpose io port circuit type function 101 ocpa0 i/o po0 a ppg output 102 ocpa1 i/o po1 a ppg output 103 ocpa2 i/o po2 a ppg output 104 ocpa3 i/o po3 a ppg output 105 vddx ?? ? ? 106 x0 ?? h 4 mhz oscillator pin 107 x1 ?? h 4 mhz oscillator pin 108 vss ?? ? ? 109 vdd ?? ? ? 110 monclk o ? q1 system clock output 111 vss ?? ? ? 112 vdd35 ?? ? separated ext. bus vdd, 3.3 or 5.0 v 113 vss ?? ? ? 114 wr3x i/o ? s ext. bus control 115 wr2x i/o ? s ext. bus control 116 wr1x i/o ? s ext. bus control 117 wr0x i/o ? s ext. bus control 118 rdy i/o ? s ext. bus control 119 vdd35 ?? ? separated ext. bus vdd, 3.3 or 5.0 v 120 vss ?? ? ? 121 d0 i/o ? q ext. bus data bit 0 122 d1 i/o ? q ext. bus data bit 1 123 d2 i/o ? q ext. bus data bit 2 124 d3 i/o ? q ext. bus data bit 3 125 d4 i/o ? q ext. bus data bit 4 126 d5 i/o ? q ext. bus data bit 5 127 d6 i/o ? q ext. bus data bit 6 128 d7 i/o ? q ext. bus data bit 7 129 d8 i/o ? q ext. bus data bit 8 130 d9 i/o ? q ext. bus data bit 9 131 d10 i/o ? q ext. bus data bit 10 132 d11 i/o ? q ext. bus data bit 11 133 d12 i/o ? q ext. bus data bit 12 134 d13 i/o ? q ext. bus data bit 13
mb91360g series 30 (continued) note : if pins vdd35 (9, 21, 40, 112, 119, 137, 155) are connected to a 3.3 v supply the external bus interface (pins 1-40, 112-160) can be operated at 3.3 v levels. pin no. pin name i/o general purpose io port circuit type function 135 d14 i/o ? q ext. bus data bit 14 136 d15 i/o ? q ext. bus data bit 15 137 vdd35 ?? ? separated ext. bus vdd, 3.3 or 5.0 v 138 vss ?? ? ? 139 d16 i/o ? q ext. bus data bit 16 140 d17 i/o ? q ext. bus data bit 17 141 d18 i/o ? q ext. bus data bit 18 142 d19 i/o ? q ext. bus data bit 19 143 d20 i/o ? q ext. bus data bit 20 144 d21 i/o ? q ext. bus data bit 21 145 d22 i/o ? q ext. bus data bit 22 146 d23 i/o ? q ext. bus data bit 23 147 d24 i/o ? q ext. bus data bit 24 148 d25 i/o ? q ext. bus data bit 25 149 d26 i/o ? q ext. bus data bit 26 150 d27 i/o ? q ext. bus data bit 27 151 d28 i/o ? q ext. bus data bit 28 152 d29 i/o ? q ext. bus data bit 29 153 d30 i/o ? q ext. bus data bit 30 154 d31 i/o ? q ext. bus data bit 31 155 vdd35 ?? ? separated ext. bus vdd, 3.3 or 5.0 v 156 vss ?? ? ? 157 a0 i/o ? q ext. bus address bit 0 158 a1 i/o ? q ext. bus address bit 1 159 a2 i/o ? q ext. bus address bit 2 160 a3 i/o ? q ext. bus address bit 3
mb91360g series 31 n i/o circuit type (continued) type circuit type remarks a ? i/o, cmos automotive schmitt-trigger input, stop control, i oh = 4 ma, i ol = 4 ma b ? i/o, cmos automotive schmitt-trigger input, analog input, stop control, i oh = 4 ma, i ol = 4 ma c ? analog output d ? analog input p n r stop control digital input digital output digital output v ss p n r r stop control digital input analog input digital output digital output v ss p n analog output v ss v cc p n r analog input v ss v cc
mb91360g series 32 (continued) type circuit type remarks e ? cmos schmitt-trigger input, pullup resistor: 50 k w f ? cmos schmitt-trigger input g ? tristate output, i oh = 4 ma, i ol = 4 ma h ? 4 mhz oscillator pin p n r digital input p v ss v ss v cc v cc p n r digital input v ss v cc p n digital output digital output v ss v cc stop control clock input x1 x0
mb91360g series 33 (continued) type circuit type remarks i ? 32 khz oscillator pin j ? i/o, cmos automotive schmitt-trigger input, stop control (led) , i oh = 14 ma, i ol = 24 ma k ? i/o, cmos automotive schmitt-trigger input, stop control (smc) , i oh = 30 ma, i ol = 30 ma ? typ slew rate of 40 ns l ? i/o, cmos input: 5 v or 3 v input, i oh = 4 ma, i ol = 4 ma stop control clock input x1a x0a p n r stop control digital input digital output digital output v ss p n r stop control digital input digital output digital output v ss p n r digital input digital output digital output v ss v cc
mb91360g series 34 (continued) type circuit type remarks m ? i/o, cmos automotive schmitt-trigger input, analog input, stop control (smc) , i oh = 30 ma, i ol = 30 ma ? typ slew rate of 40 ns n ? i/o, cmos input, pulldown resistor: 50 k w , 5 v or 3 v input, i oh = 4 ma, i ol = 4 ma o ? cmos input, pulldown resistor: 50 k w , 5 v or 3 v input p ? cmos input: 3 v input p n r r stop control digital input analog input digital output digital output v ss p n r digital input digital output digital output n v ss v cc p n r digital input n v ss v ss v cc v cc p n r digital input v ss v cc
mb91360g series 35 (continued) type circuit type remarks q/q1 ? q : i/o cmos input, stop control, i oh = 4 ma, i ol = 4 ma ? q1 : i/o cmos input, stop control, i oh = 8 ma, i ol = 8 ma s ? i/o, cmos schmitt-trigger input, stop control, pullup resistor : 10 k w , i oh = 4 ma, i ol = 4 ma t ? cmos input ? can withstand high v id for flash programming u ? cmos schmitt-trigger input, pullup resistor: 50 k w , 3 v and 5 v input to the core p n r stop control digital input digital output digital output v ss p n r p v ss v cc digital output digital output digital input stop control r control signal md input p n r digital input p v ss v ss v cc v cc
mb91360g series 36 (continued) note : symbols used in circuit types (common to all circuit diagrams) p : p channel transistor n : n channel transistor r : diffusion resistor type circuit type remarks v ? i/o, cmos schmitt-trigger input, stop control, pullup resistor: 50 k w ,, i oh = 4 ma, i ol = 4 ma w ? i/o, cmos input: 3 v input x ? tristate output, 3 v y ? i/o cmos input, stop control, i oh = 3 ma, i ol = 3 ma, in i 2 c mode operating as open drain outputs p n r p v ss v cc digital output digital output digital input stop control p n r digital input digital output digital output v ss 3 v p n digital output digital output v ss 3 v p n r stop control digital input digital output digital output v ss
mb91360g series 37 circuit type description a i/o, i oh = 4 ma / i ol = 4 ma, cmos automotive schmitt-trigger input, stop control b i/o, i oh = 4 ma / i ol = 4 ma, cmos automotive schmitt-trigger input, analog input, stop control c analog output d analog input e cmos schmitt-trigger input, pull-up resistor: 50 k w , f cmos schmitt-trigger input g tristate output, i oh = 4 ma / i ol = 4 ma h 4 mhz oscillator pin i 32 khz oscillator pin j i/o, i oh = 14 ma / i ol = 24 ma, cmos automotive schmitt-trigger input, stop control (led) k i/o, i oh = 30 ma / i ol = 30 ma, cmos automotive schmitt-trigger input, stop control, slew rate improved for emc (smc) l i/o, i oh = 4 ma / i ol = 4 ma, cmos input: 5 v or 3 v input m i/o, i oh = 30 ma / i ol = 30 ma, cmos automotive schmitt-trigger input, analog input, stop control, slew rate improved for emc (smc) n i/o, i oh = 4 ma / i ol = 4 ma, cmos input : 5 v or 3 v input, pulldown resistor: 50 k w o cmos input : 5 v or 3 v input, pulldown resistor: 50 k w p cmos input: 3 v input q i/o, i oh = 4 ma / i ol = 4 ma, cmos input, stop control q1 i/o, i oh = 8 ma / i ol = 8 ma, cmos input, stop control ravrl / avrh input s i/o, i oh = 4 ma / i ol = 4 ma, cmos input, stop control, pull-up resistor: 10 k w , t cmos input, can withstand v id for flash programming u cmos schmitt-trigger input, pull-up resistor: 50 k w , 3.3 v and 5 v inputs to core w i/o, i oh = 4 ma / i ol = 4 ma, cmos input: 3 v input x tristate output, i oh = 4 ma / i ol = 4 ma, 3 v y i/o, i oh = 3 ma / i ol = 3 ma (i 2 c) , cmos input, stop control
mb91360g series 38 n handling devices 1. preventing latch-up latch-up may occur in a cmos ic if a voltage greater than v dd or less than v ss is applied to an input or output pin or if the voltage applied between v dd and v ss exceeds the rating. if latch-up occurs, the power supply current increases rapidly resulting in thermal damage to circuit elements. therefore, ensure that maximum ratings are not exceeded in circuit operation. 2. connecting unused pins leaving unused input pins open may result in misbehavior or latch up and possible permanent damage of the device. therefore they must be tied to v dd or v ss through resistors. in this case those resistors should be more than 2 kohm. unused bidirectional pins should be set to the output state and can be left open, or the input state with the above described connection. the resistor of more than 2 kohm is used to limit currents through the protection diodes. in case of voltages at the not used pin of 0.3 v or more below v ss or 0.3 v or more above v dd currents which could cause latch-up will flow through those diodes. 3. external reset input when inputting an l level to the initx pin, hold this low level at the initx pin long enough so that after release of the low level at initx and the passing of the built in waiting time stable oscillation of the oscillation circuit is achieved. initx must be pulled low for at least 8 cycles of the 4 mhz oscillation clock. 4. power supply pins all v dd pins should be connected to the same potential (exception can be the external bus interface on f362ga and f369ga) . the analogue supply voltage (av cc ) must not be turned on before the digital supply voltage. if the external bus interface is supplied with 3.3 v this voltage also must not be turned on before the 5 v digital voltage has been switched on. if the supply voltage to the external bus interface is switched off (it may not be tristate but should be pulled low) it must be made sure that all related signals do not have a voltage higher than this pulled down supply. when multiple v dd and v ss pins are provided, be sure to connect all v dd and v ss pins to the power supply or ground externally. although pins at the same potential are connected together in the internal device design so as to prevent malfunctions such as latch-up, connecting all v dd and v ss pins appropriately minimizes unwanted radiation, prevents malfunction of strobe signals due to increases in the ground level, and keeps the overall output current rating. also, take care to connect v dd and v ss to current source in the lowest possible impedance. connection of a ceramic bypass capacitor of approximately 0.1 m f between v dd and v ss close to the device is recommended. the mb91360g series contains a regulator. to use the device with the 5-v power supply, supply 5-v power to the v cc pins and be sure to connect a bypass capacitor of 10 m f parallel to 10 nf to the v cc 3c pin for the regulator. 5 v 5 v 10 m f 10 nf v cc 3c v cc av cc avrh av ss v ss gnd [use with 5-v power supply]
mb91360g series 39 5. crystal oscillator circuit noise in the vicinity of the x0 and x1 pins can be a cause of device malfunction. design the circuit board so that x0, x1, the crystal oscillator (or ceramic oscillator) , and the bypass capacitor to ground are located as close to the device as possible. a printed circuit board design that surrounds the x0 and x1 pins with ground provides for stable operation and is strongly recommended. 6. mode pins connect the mode pins (md0 to md2) directly to v dd or v ss . to prevent the device unintentionally entering test mode due to noise, lay out the printed circuit board so as to minimize the distance from the mode pins to v dd or v ss and to provide a low-impedance connection. 7. turning the power supply on immediately after power on always execute init at the initx pin (start with a low level at the initx pin) . hold this low level at the initx pin long enough so that after release of the low level at initx and the passing of the built in waiting time stable oscillation of the oscillation circuit is achieved. initx must be pulled low for at least 8 cycles of the 4 mhz oscillation clock. the analogue supply voltage (av cc ) must not be turned on before the digital supply voltage. if the external bus interface is supplied with 3.3 v this voltage also must not be turned on before the 5 v digital voltage has been switched on. 8. a state in turning power on as long as the minimum operating voltage has not been reached during power-on the output pin levels are not guaranteed.
mb91360g series 40 n block diagram 32 32 32 16 32 32 clock generation FR50 core watchdog timer user ram d-bus bit search module dma controller instruction cache/ram f-bus ram bus converter boot rom 2 kb r-bus adapter sio prescaler/ sio u-timer/ uart power down reset subclock calibration external bus interface can dac adc external interrupt flash- memory i 2 c reload timer icu led sound generator alarm comparator freerunning timer real time clock voltage regulator ocu stepper motor control prog. pulse generator external bus
mb91360g series 41 n cpu core 1. memory space internal memory area 00 : 0000 00 : 03ff 00 : 07ff 00 : 1000 00 : 1024 01 : 1000 01 : 1fff 03 : c000 03 : ffff 04 : 0000 04 : 3fff 05 : 0000 05 : 07ff 08 : 0000 0f : 4000 0f : ffff 10 : 0000 128 k 128 k 128 k 64 k 16 k 16 k 32 k can fixed reset vector bootsector flash memory on f-bus boot rom f-bus ram d-bus ram i-ram dma io area direct direct (short) addressing 0..0ff : byte access 0..1ff : halfword access (16 bit) 0..3ff : word access (32 bit) 03 : d000 - 03 : ffff on f362ga 04 : 0000 - 04 : 0fff on f362ga 10 : 07ff addresses for can depend on set- tings for the chip select areas cs7. the addresses given here are valid for the cs7 settings done in the boot rom.
mb91360g series 42 2. dedicated registers each of the dedicated registers is used for a particular purpose. the dedicated registers consist of the program counter (pc) , program status (ps) , table base register (tbr) , return pointer (rp) , system stack pointer (ss p) , user stack pointer (usp) , and multiplication and division result registers (mdh/mdl) . (1) program status (ps) pc ps tbr rp ssp usp mdh mdl xxxx xxxx h (indeterminate) xxxx xxxx h (indeterminate) xxxx xxxx h (indeterminate) xxxx xxxx h (indeterminate) xxxx xxxx h (indeterminate) 0000 0000 h 000f fc00 h 32 bits program counter program status table base register return pointer system stack pointer user stack pointer multiplication and division results resisters initial value 31 bit position 20 16 ilm scr ccr 10 7 8 0 ? ? ccr : condition code register scr : system condition code register ilm : interrupt level mask
mb91360g series 43 (2) condition code register (ccr) (3) system condition code register (scr) (4) interrupt level mask register (ilm) (bit) initial value --00xxxx b 76543210 ?? sinzvc (bit) initial value xx0 b 10 9 8 d1 d0 t (bit) initial value 01111 b 20 19 18 17 16 ilm4 ilm3 ilm2 ilm1 ilm0
mb91360g series 44 3. general-purpose registers the general-purpose registers are cpu registers r0 to r15. the register are used as the accumulator for operations and as pointers (a field indicating an address) for memory access. the user can specify the purpose for which the general-purpose registers are used. among 16 general-purpose registers, the following registers assume a special purpose. this enhances some instructions. the initial value of r0 to r14 after a reset is indeterminate. the initial value of r15 is 00000000 h (ssp value) . r13 : virtual accumulator (ac) r14 : frame pointer (fp) r15 : stack pointer (sp) r0 r1 r12 r13 r14 r15 ac (accumulator) fp (frame pointer) sp (stack pointer) xxxx xxxx h xxxx xxxx h 0000 0000 h 32-bits initial value register bank structure
mb91360g series 45 n mode setting the FR50 series of devices uses mode pins (md2 to md0) and a mode register (modr) to set the operation mode. (1) mode pins three mode pins (md2 to md0) are used to specify the reset mode vector access area. (2) mode register (modr) the data to be written to 0000_7fdh using mode vector fetch is called mode data. modr is located at 0000_07fdh. after an operation mode has been set in modr, the device operates in this operation mode. modr is set only when a reset factor (init level) occurs. user programs cannot write data to modr. < mode register (modr) > [bits 7 to 3] : (reserved bits) always set 00000 at bits 7 to 3. operation is not guaranteed when other values are set. [bit 2] : roma (internal rom enable bit) the roma bit is used to set whether to validate the internal rom area (fbus memory area) . mode pins mode name reset vector access area remarks md2 md1 md0 0 0 0 internal rom mode vector internal 0 0 1 external rom mode vector external the mode register is used to set the bus width. remaining settings ?? reserved roma function remarks 0 external rom mode access to the fbus area is external. 1 internal rom mode address initial value 0000 07fd h xxxxxxxx 76543210 0 0 0 0 0 roma wth1 operation mode setting bit wth0
mb91360g series 46 [bits 1 and 0] : wth1 and wth0 (bus width/single chip mode specifying bits) the wth1 and wth0 bits are used to set the bus width (valid when operation mode is external bus mode) and the single chip mode. when the operation mode is the external bus mode, this value is set at the bw1 and bw0 bits of amd0 (cs0 area) . (3) fixed vector if mb91360 series devices are started in mode md[2 : 0] = 000, the internal fixed mode vector (fmv = 0x06) and the fixed reset vector are used. the fixed reset vector points to the start address of the internal boot rom. this enables access to the f-bus area, to the internal can modules and the internal flash memory. see also section boot rom. wth1 wth0 function remarks 0 0 8-bit bus width external bus mode 0 1 16-bit bus width external bus mode 1 0 32-bit bus width external bus mode 1 1 single chip mode
mb91360g series 47 n i/o map ? how to read the i/o map read/write attribute register initial value after a reset (bit initial values) 1 : initial value 1, 0 : initial value 0, x : initial value x (indeterminate) , ? indicates non-existent bits register name (the register in column 1 is at location 4n, the register in column 2 at 4n + 1, and so on.) location of far left of register ( + 0) . + 1 + 2, and + 3 each increment the loca- tion by one. when performing word access, the register in column 1 is placed at the msb end of the data. precautions : ? do not use rmw instructions on registers containing write-only (w) bits. rmw instructions (rmw : read-modify-write) and rj, @ri or rj, @ri eor rj, @ri andh rj, @ri orh rj, @ri eorh rj, @ri andb rj, @ri orb rj, @ri eorb rj, @ri bandl #u4, @ri borl #u4, @ri beorl #u4, @ri bandh #u4, @ri borh #u4, @ri beorh #u4, @ri ? the data in reserved areas and areas marked ? is indeterminate. do not use those ares ! address register internal peripheral + + + + 0 + + + + 1 + + + + 2 + + + + 3 000014 h pdrg[r/w] pdrh[r/w] pdri[r/w] ? port data register xxxxxxxx xxxxxxxx - - - - xxxx
mb91360g series 48 (continued) address register block + + + + 0 + + + + 1 + + + + 2 + + + + 3 000000 h reserved reserved reserved reserved t-unit port data register 000004 h reserved reserved reserved pdr7 [r/w] -111 - - - - 000008 h pdr8 [r/w] xxxxxxxx pdr9 [r/w] xxxxxxx1 ? pdrb [r/w] - - - - - xxx 00000c h ? 000010 h pdrg [r/w] xxxxxxxx pdrh [r/w] xxxxxxxx pdri [r/w] x - - - x - - - pdrj [r/w] xxxxxxxx r-bus port data register 000014 h pdrk [r/w] xxxxxxxx pdrl [r/w] xxxxxxxx pdrm [r/w] - - - - xxxx pdrn [r/w] - - xxxxxx 000018 h pdro [r/w] xxxxxxxx pdrp [r/w] - - xxxxx pdrq [r/w] - - xxxxx pdrr [r/w] xxxxxxxx 00001c h pdrs [r/w] xxxxxxxx ??? 000020 h to 00003c h ? reserved 000040 h eirr [r/w] 00000000 enir [r/w] 00000000 elvr [r/w] 00000000 00000000 ext int/nmi 000044 h dicr [r/w] - - - - - - - 0 hrcl [r/w, r] 0 - - 11111 clkr2 [r/w] - - - - - 000 reserved dlyi/i-unit rtc 000048 h tmrlr0 [w] xxxxxxxx xxxxxxxx tmr0 [r] xxxxxxxx xxxxxxxx reload timer 0 00004c h ? tmcsr0 [r/w] - - - - 0000 - - - 00000 000050 h tmrlr1 [w] xxxxxxxx xxxxxxxx tmr1 [r] xxxxxxxx xxxxxxxx reload timer 1 000054 h ? tmcsr1 [r/w] - - - - 0000 - - - 00000 000058 h tmrlr2 [w] xxxxxxxx xxxxxxxx tmr2 [r] xxxxxxxx xxxxxxxx reload timer 2 00005c h ? tmcsr2 [r/w] - - - - 0000 - - - 00000 000060 h ssr0 [r/w] 00001 - 00 sidr0 [r/w] xxxxxxxx scr0 [r/w, w] 00000100 smr0 [r/w, w] 00 - - 0 - 0 - uart0 000064 h uls0 [r/w] - - - - 0000 ???
mb91360g series 49 (continued) address register block + + + + 0 + + + + 1 + + + + 2 + + + + 3 000068 h utim0/utimr0 [r/w] 00000000 00000000 drcl0 [w] - - - - - - - - utimc0 [r/w] 0 - - - 0 - 01 u-timer 0 00006c h ssr1 [r/w, r] 00001 - 00 sidr1 [r/w] xxxxxxxx scr1 [r/w, w] 00000100 smr1 [r/w, w] 00 - - 0 - 0 - uart1 000070 h uls1 [r/w] - - - - 0000 ??? 000074 h utim1/utimr1 [r/w] 00000000 00000000 drcl1 [w] - - - - - - - - utimc1 [r/w] 0 - - - - - 01 u-timer 1 000078 h ssr2 [r/w, r] 00001 - 00 sidr2 [r/w] xxxxxxxx scr2 [r/w, w] 00000100 smr2 [r/w, w] 00 - - 0 - 0 - uart2 00007c h uls2 [r/w] - - - - 0000 ??? 000080 h utim2/utimr2 [r/w] 00000000 00000000 drcl2 [w] - - - - - - - - utimc2 [r/w] 0 - - - 0 - 01 u-timer2 000084 h smcs0 [r/w, r] 00000010 - - - - 00-0 ses0 [r/w] - - - - - - 00 sdr0 [r/w] 00000000 sio 0 000088 h smcs1 [r/w, r] 00000010 - - - - 00 - 0 ses1 [r/w] - - - - - - 00 sdr1 [r/w] 00000000 sio 1 00008c h cdcr0 [r/w] 0 - - - 1111 reserved cdcr1 [r/w] 0 - - - 1111 reserved sio 0/1 prescaler 000090 h ? reserved 000094 h ibcr [r/w] 00000000 ibsr [r] 00000000 iadr [r/w] -xxxxxxx iccr [r/w] - - 0xxxxx i 2 c (old) ? new i 2 c from addr 0x184 000098 h ? idar [r/w] xxxxxxxx ? idbl [r/w] - - - - - - - 0 00009c h admd [r/w, w] - - - x0000 adch [r/w] 00000000 ? adcs [r/w, w] 0000 - - 00 a/d converter 0000a0 h adcd [r/w] 000000xx xxxxxxxx ? adbl [r/w] - - - - - - - 0 0000a4 h ? dacr [r/w] - - - - - 000 dadr0 [r/w] - - - - - - xx xxxxxxxx dac 0000a8 h dadr1 [r/w] - - - - - - xx xxxxxxxx ? ddbl [r/w] - - - - - - - 0 0000ac h iotdbl0 [r/w] - - - - - 000 ics01 [r/w] 00000000 iotdbl1 [r/w] - - - - - 000 ics23 [r/w] 00000000 input capture 0, 1, 2, 3 0000b0 h ipcp0 [r] xxxxxxxx xxxxxxxx ipcp1 [r] xxxxxxxx xxxxxxxx 0000b4 h ipcp2 [r] xxxxxxxx xxxxxxxx ipcp3 [r] xxxxxxxx xxxxxxxx
mb91360g series 50 (continued) address register block + + + + 0 + + + + 1 + + + + 2 + + + + 3 0000b8 h ocs01 [r/w] - - - 0 - - 00 0000 - - 00 reserved output compare 0, 1, 2.3 0000bc h occp0 [r/w] xxxxxxxx xxxxxxxx occp1 [r/w] xxxxxxxx xxxxxxxx 0000c0 h occp2 [r/w] xxxxxxxx xxxxxxxx occp3 [r/w] xxxxxxxx xxxxxxxx 0000c4 h ? reserved 0000c8 h tcdt0 [r/w] xxxxxxxx xxxxxxxx ? tccs0 [r/w] - 0000000 free running counter 0 for icu/ocu 0000cc h tcdt1 [r/w] xxxxxxxx xxxxxxxx ? tccs1 [r/w] - 0000000 free running counter 1 for icu/ocu 0000d0 h zpd0 [r/w] 00000010 pwc0 [r/w] - - 000 - - 0 zpd1 [r/w] 00000010 pwc1 [r/w] 00000 - - 0 smc 0, 1 0000d4 h zpd2 [r/w] 00000010 pwc2 [r/w] - - 000 - - 0 zpd3 [r/w] 00000010 pwc3 [r/w] 00000 - - 0 smc 2, 3 0000d8 h pwc20 [r/w] xxxxxxxx pwc10 [r/w] xxxxxxxx pws20 [r/w] - 0000000 pws10 [r/w] - - 000000 smc 0 0000dc h pwc21 [r/w] xxxxxxxx pwc11 [r/w] xxxxxxxx pws21 [r/w] - 0000000 pws11 [r/w] - - 000000 smc 1 0000e0 h pwc22 [r/w] xxxxxxxx pwc12 [r/w] xxxxxxxx pws22 [r/w] - 0000000 pws12 [r/w] - - 000000 smc 2 0000e4 h pwc23 [r/w] xxxxxxxx pwc13 [r/w] xxxxxxxx pws23 [r/w] - 0000000 pws13 [r/w] - - 000000 smc 3 0000e8 h smdbl0 [r/w] - - - - - - - 0 smdbl1 [r/w] - - - - - - 0 smdbl2 [r/w] - - - - - - - 0 smdbl3 [r/w] - - - - - - - 0 smc 0, 1, 2, 3 0000ec h ? sgdbl [r/w] - - - - - - - 0 sgcr [r/w, r] 0 - - - - - 00 000 - - 000 sound generator 0000f0 h sgar [r/w] 00000000 sgfr [r/w] xxxxxxxx sgtr [r/w] xxxxxxxx sgdr [r/w] xxxxxxxx 0000f4 h ? wtdbl [r/w] - - - - - - - 0 wtcr [r/w, r] 00000000 000 - 0000 real time clock (watchtimer) 0000f8 h ? wtbr [r/w] - - xxxxxx xxxxxxxx xxxxxxxx 0000fc h wthr [r/w] - - - 00000 wtmr [r/w] - - 000000 wtsr [r/w] - - 000000 ? 000100 h tmrlr3 [w] xxxxxxxx xxxxxxxx tmr3 [r] xxxxxxxx xxxxxxxx reload timer 3 000104 h ? tmcsr3 [r/w] - - - - xx - - - - - xxxxx
mb91360g series 51 (continued) address register block + + + + 0 + + + + 1 + + + + 2 + + + + 3 000108 h tmrlr4 [w] xxxxxxxx xxxxxxxx tmr4 [r] xxxxxxxx xxxxxxxx reload timer 4 00010c h ? tmcsr4 [r/w] - - - - xx - - - - - xxxxx 000110 h tmrlr5 [w] xxxxxxxx xxxxxxxx tmr5 [r] xxxxxxxx xxxxxxxx reload timer 5 000114 h ? tmcsr5 [r/w] - - - - xx - - - - - xxxxx 000118 h gcn10 [r/w] 00110010 00010000 pdbl0 [r/w] - - - 00000 gcn20 [r/w] - - - - 0000 pwm control 0 00011c h gcn11 [r/w] 00110010 00010000 pdbl1 [r/w] - - - 00000 gcn21 [r/w] - - - - 0000 pwm control 1 000120 h ptmr0 [r] 11111111 11111111 pcsr0 [w] xxxxxxxx xxxxxxxx pwm0 000124 h pdut0 [w] xxxxxxxx xxxxxxxx pcnh0 [r/w] 0000000 - pcnl0 [r/w] 000000 - 0 000128 h ptmr1 [r] 11111111 11111111 pcsr1 [w] xxxxxxxx xxxxxxxx pwm1 00012c h pdut1 [w] xxxxxxxx xxxxxxxx pcnh1 [r/w] 0000000 - pcnl1 [r/w] 000000 - 0 000130 h ptmr2 [r] 11111111 11111111 pcsr2 [w] xxxxxxxx xxxxxxxx pwm2 000134 h pdut2 [w] xxxxxxxx xxxxxxxx pcnh2 [r/w] 0000000 - pcnl2 [r/w] 000000 - 0 000138 h ptmr3 [r] 11111111 11111111 pcsr3 [w] xxxxxxxx xxxxxxxx pwm3 00013c h pdut3 [w] xxxxxxxx xxxxxxxx pcnh3 [r/w] 0000000 - pcnl3 [r/w] 000000 - 0 000140 h ptmr4 [r] 11111111 11111111 pcsr4 [w] xxxxxxxx xxxxxxxx pwm4 000144 h pdut4 [w] xxxxxxxx xxxxxxxx pcnh4 [r/w] 0000000 - pcnl4 [r/w] 000000 - 0 000148 h ptmr5 [r] 11111111 11111111 pcsr5 [w] xxxxxxxx xxxxxxxx pwm5 00014c h pdut5 [w] xxxxxxxx xxxxxxxx pcnh5 [r/w] 0000000 - pcnl5 [r/w] 000000 - 0 000150 h ptmr6 [r] 11111111 11111111 pcsr6 [w] xxxxxxxx xxxxxxxx pwm6 000154 h pdut 6 [w] xxxxxxxx xxxxxxxx pcnh6 [r/w] 0000000 - pcnl6 [r/w] 000000 - 0
mb91360g series 52 * : old and new i 2 c share this bit. (continued) address register block + + + + 0 + + + + 1 + + + + 2 + + + + 3 000158 h ptmr7 [r] 11111111 11111111 pcsr7 [w] xxxxxxxx xxxxxxxx pwm7 00015c h pdut7 [w] xxxxxxxx xxxxxxxx pcnh7 [r/w] 0000000 - pcnl7 [r/w] 000000 - 0 000160 h ? reserved 000164 h cmcr [r/w] 11111111 0000000 cmpr [r/w] - - - -1001 1 - - -0001 clock modulation 000168 h cmls0 [r/w] 01110111 1111111 cmls1 [r/w] 01110111 1111111 00016c h cmls2 [r/w] 01110111 1111111 cmls3 [r/w] 01110111 1111111 000170 h cmlt0 [r/w, r] - - - - -100 00000010 cmlt1 [r/w, r] 11110100 00000010 000174 h cmlt2 [r/w] - - - - -100 00000010 cmlt3 [r/w, r] - - - - -100 00000010 000178 h cmac [r/w] 11111111 1111111 cmts [r] - -000001 01111111 00017c h ? pdrcr [r/w] - - - - - 000 ?? power down reset 000180 h accdbl[r/w] - - - - - - - 0 acsr [r/w, r] - - - xxx00 ?? alarm comparator 000184 h ibcr2 [r/w] 00000000 ibsr2 [r] 00000000 itbah [r/w] - - - - - - 00 itbal [r/w] 00000000 i 2 c (new) (*) old and new i 2 c share this bit ! 000188 h itmkh [r/w, r] 00 - - - - 11 itmkl [r/w] 11111111 ismk [r/w] 01111111 isba [r/w] - 0000000 00018c h idarh [-] 00000000 idar2 [r/w] 00000000 iccr2 [r/w] - 0011111 idbl2 (*) [r/w] - - - - - - - 0 000190 h cucr [r/w, r] - - - - - - - - - - - 0 - -00 cutd [r/w] 10000000 00000000 calibration unit of 32 khz oscillator 000194 h cutr1 [r] - - - - - - - - 00000000 cutr2 [r] 00000000 00000000 000198 h to 0001f8 h ? reserved 0001fc h ?? f362md [r/w] 00000000 ? f362 mode register 000200 h dmaca0 [r/w] 00000000 0000xxxx xxxxxxxx xxxxxxxx dmac 000204 h dmacb0 [r/w] 00000000 00000000 xxxxxxxx xxxxxxxx
mb91360g series 53 (continued) address register block + + + + 0 + + + + 1 + + + + 2 + + + + 3 000208 h dmaca1 [r/w] 00000000 0000xxxx xxxxxxxx xxxxxxxx dmac 00020c h dmacb1 [r/w] 00000000 00000000 xxxxxxxx xxxxxxxx 000210 h dmaca2 [r/w] 00000000 0000xxxx xxxxxxxx xxxxxxxx 000214 h dmacb2 [r/w] 00000000 00000000 xxxxxxxx xxxxxxxx 000218 h dmaca3 [r/w] 00000000 0000xxxx xxxxxxxx xxxxxxxx 00021c h dmacb3 [r/w] 00000000 00000000 xxxxxxxx xxxxxxxx 000220 h dmaca4 [r/w] 00000000 0000xxxx xxxxxxxx xxxxxxxx 000224 h dmacb4 [r/w] 00000000 00000000 xxxxxxxx xxxxxxxx 000228 h to 00023c h ? 000240 h dmacr [r/w] 00 - - 0000 - - - - - - - - - - - - - - - - - - - - - - - - 000244 h to 0002fc h ? reserved 000300 h irbs [r/w, r] 00000000 00000001 00100000 - - - - - - - - instruction cache 000304 h ? isize [r/w] - - - - - -11 000308 h to 0003e0 h ? reserved 0003e4 h ? ichrc [r/w] 0-000000 instruction cache 0003e8 h to 0003ec h ? reserved
mb91360g series 54 (continued) address register block + + + + 0 + + + + 1 + + + + 2 + + + + 3 0003f0 h bsd0 [w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx bit search module 0003f4 h bsd1 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0003f8 h bsdc [w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0003fc h bsrr [r] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000400 h ddrg [r/w] 00000000 ddrh [r/w] 00000000 ddri [r/w] - - - -0- - - ddrj [r/w] 00000000 r-bus port direction register 000404 h ddrk [r/w] 00000000 ddrl [r/w] 00000000 ddrm [r/w] - - - -0000 ddrn [r/w] - -000000 000408 h ddro [r/w] 00000000 ddrp [r/w] - - - -0000 ddrq [r/w] - -000000 ddrr [r/w] 00000000 00040c h ddrs [r/w] 00000000 ??? 000410 h pfrg [r/w] 00000000 pfrh [r/w] 00000000 pfri [r/w] - - - -0- - - pfrj [r/w] 00000000 r-bus port function register 000414 h pfrk [r/w] 00000000 pfrl [r/w] 00000000 pfrm [r/w] - - - -0000 pfrn [r/w] - -000000 000418 h pfro [r/w] 00000000 pfrp [r/w] 00000000 pfrq [r/w] - -000000 pfrr [r/w] 00000000 00041c h pfrs [r/w] 00000000 ??? 000420 h to 00043c h ? reserved 000440 h icr00 [r/w, r] - - -11111 icr01 [r/w, r] - - -11111 icr02 [r/w, r] - - -11111 icr03 [r/w, r] - - -11111 interrupt control unit 000444 h icr04 [r/w, r] - - -11111 icr05 [r/w, r] - - -11111 icr06 [r/w, r] - - -11111 icr07 [r/w, r] - - -11111 000448 h icr08 [r/w, r] - - -11111 icr09 [r/w, r] - - -11111 icr10 [r/w, r] - - -11111 icr11 [r/w, r] - - -11111 00044c h icr12 [r/w, r] - - -11111 icr13 [r/w, r] - - -11111 icr14 [r/w, r] - - -11111 icr15 [r/w, r] - - -11111 000450 h icr16 [r/w, r] - - -11111 icr17 [r/w, r] - - -11111 icr18 [r/w, r] - - -11111 icr19 [r/w, r] - - -11111 000454 h icr20 [r/w, r] - - -11111 icr21 [r/w, r] - - -11111 icr22 [r/w, r] - - -11111 icr23 [r/w, r] - - -11111 000458 h icr24 [r/w, r] - - -11111 icr25 [r/w, r] - - -11111 icr26 [r/w, r] - - -11111 icr27 [r/w, r] - - -11111
mb91360g series 55 (continued) address register block + + + + 0 + + + + 1 + + + + 2 + + + + 3 00045c h icr28 [r/w, r] - - -11111 icr29 [r/w, r] - - -11111 icr30 [r/w, r] - - -11111 icr31 [r/w, r] - - -11111 interrupt control unit 000460 h icr32 [r/w, r] - - -11111 icr33 [r/w, r] - - -11111 icr34 [r/w, r] - - -11111 icr35 [r/w, r] - - -11111 000464 h icr36 [r/w, r] - - -11111 icr37 [r/w, r] - - -11111 icr38 [r/w, r] - - -11111 icr39 [r/w, r] - - -11111 000468 h icr40 [r/w, r] - - -11111 icr41 [r/w, r] - - -11111 icr42 [r/w, r] - - -11111 icr43 [r/w, r] - - -11111 00046c h icr44 [r/w, r] - - -11111 icr45 [r/w, r] - - -11111 icr46 [r/w, r] - - -11111 icr47 [r/w, r] - - -11111 000470 h to 00047c h ? reserved 000480 h rsrr [r/w, r] 10000000 stcr [r/w] 00110011 tbcr [r/w] x0000x00 ctbr [w] xxxxxxxx clock control unit 000484 h clkr [r/w] 00000000 wpr [w] xxxxxxxx divr0 [r/w] 00000011 divr1 [r/w] 00000000 000488 h to 0005fc h ? reserved 000600 h ???? t-unit port direction register 000604 h ??? ddr7 [r/w] 00000000 000608 h ddr8 [r/w] 00000000 ddr9 [r/w] 00000000 ? ddrb [r/w] 00000000 00060c h ? 000610 h ???? t-unit port function register 000614 h ??? pfr7 [r/w] 00001111 000618 h pfr8 [r/w] 111110-0 pfr9 [r/w] 11110101 ? pfrb [r/w] 00000000 00061c h ? 000620 h ? 000624 h ? pfr27 [r/w] 1111-00- 000628 h to 00063f h ? reserved
mb91360g series 56 (continued) address register block + + + + 0 + + + + 1 + + + + 2 + + + + 3 000640 h asr0 [w] 00000000 00000000 amr0 [w] 11111000 11111111 t-unit 000644 h asr1 [w] 00000000 00000000 amr1 [w] 00000000 00000000 000648 h asr2 [w] 00000000 00000000 amr2 [w] 00000000 00000000 00064c h asr3 [w] 00000000 00000000 amr3 [w] 00000000 00000000 000650 h asr4 [w] 00000000 00000000 amr4 [w] 00000000 00000000 000654 h asr5 [w] 00000000 00000000 amr5 [w] 00000000 00000000 000658 h asr6 [w] 00000000 00000000 amr6 [w] 00000000 00000000 00065c h asr7 [w] 00000000 00000000 amr7 [w] 00000000 00000000 000660 h amd0 [r/w] -00xx111 amd1 [r/w] -xxxxxxx amd2 [r/w] - -xxxxxx amd3 [r/w] - -xxxxxx 000664 h amd4 [r/w] - -xxxxxx amd5 [r/w] - -xxxxxx amd6 [r/w] -xxxxxxx amd7 [r/w] -xxxxxxx 000668 h cse 11000011 ??? 00066c h ?? 000670 h che 11111111 ?? 000674 h to 0007f8 h ? reserved 0007fc h ? modr [w] xxxxxxxx ?? mode register 000800 h to 000afc h ? reserved
mb91360g series 57 (continued) address register block + + + + 0 + + + + 1 + + + + 2 + + + + 3 000b00 h ests0 x0000000 ests1 xxxxxxxx ests2 xxxxxxxx ? dsu 000b04 h ectl0 0x000000 ectl1 00000000 ectl2 000x0000 ectl3 00000x11 000b08 h ecnt0 xxxxxxxx ecnt1 xxxxxxxx eusa xxx0000x edtc 0000xxxx 000b0c h ewpt xxxxxxxx xxxxxxxx ? 000b10 h edtr0 xxxxxxxx xxxxxxxx edtr1 xxxxxxxx xxxxxxxx 000b14 h to 000b1c h ? 000b20 h eia0 xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000b24 h eia1 xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000b28 h eia2 xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000b2c h eia3 xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000b30 h eia4 xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000b34 h eia5 xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000b38 h eia6 xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000b3c h eia7 xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000b40 h edta xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000b44 h edtm xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000b48 h eoa0 xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000b4c h eoa1 xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000b50 h epcr xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000b54 h epsr xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx
mb91360g series 58 (continued) address register block + + + + 0 + + + + 1 + + + + 2 + + + + 3 000b58 h eiam0 xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx dsu 000b5c h eiam1 xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000b60 h eoam0/eodm0 xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000b64 h eoam1/eodm1 xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000b68 h eod0 xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000b6c h eod1 xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 001000 h dmasa0 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx dmac 001004 h dmada0 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 001008 h dmasa1 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 00100c h dmada1 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 001010 h dmasa2 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 001014 h dmada2 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 001018 h dmasa3 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 00101c h dmada3 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 001020 h dmasa4 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 001024 h dmada4 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 001028 h to 003ffc h ? reserved 004000 h to 006fff h ? reserved
mb91360g series 59 (continued) address register block + + + + 0 + + + + 1 + + + + 2 + + + + 3 007000 h fmcs [r/w] 1110x000 ??? flash memory control register 007004 h fmwt [r/w] - -000011 ??? 007008 h to 00fffc h ? reserved 010000 h to 010ffc h (for exact address range see chapter about i-cache) on f362ga and f369ga no cache, but 4 k i-ram are available i-cache 4 kb 011000 h to 011ffc h ? reserved 012000 h to 01fffc h ? reserved 020000 h to 03bffc h ? reserved 03c000 h to 03fffc h only first 12 kb are available on f362ga user ram 16 kb (d-bus) 040000 h to 043ffc h only first 4 k are available on f362ga fast ram 16 kb (f-bus) 044000 h to 0feffc ? reserved 050000 h to 0507fc h ? boot rom 2 kb (f-bus) 050800 h to 07fff4 h ? reserved
mb91360g series 60 (continued) address register block + + + + 0 + + + + 1 + + + + 2 + + + + 3 080000 h to 09fffc h sector 0 64 kb sector 7 64 kb flash memory 512 k on f-bus 0a0000 h to 0bfffc sector 1 64 kb sector 8 64 kb 0c0000 h to 0dfffc sector 2 64 kb sector 9 64 kb 0e0000 h to 0efffc sector 3 32 kb sector 10 32 kb 0f0000 h to 0f3ffc h sector 4 8 kb sector 11 8 kb 0f4000 h to 0f7ffc h sector 5 8 kb sector 12 8 kb 0f8000 h to 0ffff4 h sector 6 16 kb sector 13 16 kb 0ffff8 h fmv [r] 06 00 00 00 h fixed reset/mode vector 0ffffc h frv [r] 00 05 00 00 h write operations to address 0ffff8 h and 0ffffc h are not possible. when reading these addresses, the values shown above will be read.
mb91360g series 61 (continued) address register block + + + + 0 + + + + 1 + + + + 2 + + + + 3 100000 h bvalr0 [r/w] 00000000 00000000 treqr0 [r/w] 00000000 00000000 can 0 remark : address range for can 0 to can 3 depends on chip select range. mentioned addresses are default values, determined by boot rom contents. 100004 h tcanr0 [w] 00000000 00000000 tcr0 [r/w] 00000000 00000000 100008 h rcr0 [r/w] 00000000 00000000 rrtrr0 [r/w] 00000000 00000000 10000c h rovrr0 [r/w] 00000000 00000000 rier0 [r/w] 00000000 00000000 100010 h csr0 [r/w, r] 00000000 00000001 ? leir0 [r/w] 000-0000 100014 h rtec0 [r] 00000000 00000000 btr0 [r/w] -1111111 11111111 100018 h ider0 [r/w] xxxxxxxx xxxxxxxx trtrr0 [r/w] 00000000 00000000 10001c h rfwtr0 [r/w] xxxxxxxx xxxxxxxx tier0 [r/w] 00000000 00000000 100020 h amsr0 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 100024 h amr00 [r/w] xxxxxxxx xxxxxxxx xxxxx - - - xxxxxxxx 100028 h amr10 [r/w] xxxxxxxx xxxxxxxx xxxxx - - - xxxxxxxx 10002c h to 100048 h general purpose ram [r/w] 10004c h idr00 [r/w] xxxxxxxx xxxxxxxx xxxxx - - - xxxxxxxx 100050 h idr10 [r/w] xxxxxxxx xxxxxxxx xxxxx - - - xxxxxxxx 100054 h idr20 [r/w] xxxxxxxx xxxxxxxx xxxxx - - - xxxxxxxx 100058 h idr30 [r/w] xxxxxxxx xxxxxxxx xxxxx - - - xxxxxxxx 10005c h idr40 [r/w] xxxxxxxx xxxxxxxx xxxxx - - - xxxxxxxx 100060 h idr50 [r/w] xxxxxxxx xxxxxxxx xxxxx - - - xxxxxxxx 100064 h idr60 [r/w] xxxxxxxx xxxxxxxx xxxxx - - - xxxxxxxx 100068 h idr70 [r/w] xxxxxxxx xxxxxxxx xxxxx - - - xxxxxxxx can 0
mb91360g series 62 (continued) address register block + + + + 0 + + + + 1 + + + + 2 + + + + 3 10006c h idr80 [r/w] xxxxxxxx xxxxxxxx xxxxx - - - xxxxxxxx can 0 100070 h idr90 [r/w] xxxxxxxx xxxxxxxx xxxxx - - - xxxxxxxx 100074 h idr100 [r/w] xxxxxxxx xxxxxxxx xxxxx - - - xxxxxxxx 100078 h idr110 [r/w] xxxxxxxx xxxxxxxx xxxxx - - - xxxxxxxx 10007c h idr120 [r/w] xxxxxxxx xxxxxxxx xxxxx - - - xxxxxxxx 100080 h idr130 [r/w] xxxxxxxx xxxxxxxx xxxxx - - - xxxxxxxx 100084 h idr140 [r/w] xxxxxxxx xxxxxxxx xxxxx - - - xxxxxxxx 100088 h idr150 [r/w] xxxxxxxx xxxxxxxx xxxxx - - - xxxxxxxx 10008c h dlcr00 [r/w] - - - - - - - - - - - - xxxx dlcr10 [r/w] - - - - - - - - - - - - xxxx 100090 h dlcr20 [r/w] - - - - - - - - - - - - xxxx dlcr30 [r/w] - - - - - - - - - - - - xxxx 100094 h dlcr40 [r/w] - - - - - - - - - - - - xxxx dlcr50 [r/w] - - - - - - - - - - - - xxxx 100098 h dlcr60 [r/w] - - - - - - - - - - - - xxxx dlcr70 [r/w] - - - - - - - - - - - - xxxx 10009c h dlcr80 [r/w] - - - - - - - - - - - - xxxx dlcr90 [r/w] - - - - - - - - - - - - xxxx 1000a0 h dlcr100 [r/w] - - - - - - - - - - - - xxxx dlcr110 [r/w] - - - - - - - - - - - - xxxx 1000a4 h dlcr120 [r/w] - - - - - - - - - - - - xxxx dlcr130 [r/w] - - - - - - - - - - - - xxxx 1000a8 h dlcr140 [r/w] - - - - - - - - - - - - xxxx dlcr150 [r/w] - - - - - - - - - - - - xxxx 1000ac h dtr00 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 1000b4 h dtr10 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 1000bc h dtr20 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx
mb91360g series 63 (continued) address register block + + + + 0 + + + + 1 + + + + 2 + + + + 3 1000c4 h dtr30 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx can 0 1000cc h dtr40 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 1000d4 h dtr50 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 1000dc h dtr60 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 1000e4 h dtr70 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 1000ec h dtr80 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 1000f4 h dtr90 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 1000fc h dtr100 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 100104 h dtr110 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 10010c h dtr120 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 100114 h dtr130 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 10011c h dtr140 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 100124 h dtr150 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 10012c h creg0 [r/w] 00000000 00000110 ?
mb91360g series 64 (continued) address register block + + + + 0 + + + + 1 + + + + 2 + + + + 3 100200 h bvalr1 [r/w] 00000000 00000000 ? treqr1 [r/w] 00000000 00000000 ? can 1 remark : address range for can 0 to can 3 depends on chip select range. mentioned addresses are default values, determined by boot rom contents. 100204 h tcanr1 [w] 00000000 00000000 tcr1 [r/w] 00000000 00000000 100208 h rcr1 [r/w] 00000000 00000000 rrtrr1 [r/w] 00000000 00000000 10020c h rovrr1 [r/w] 00000000 00000000 rier1 [r/w] 00000000 00000000 100210 h csr1 [r/w, r] 00000000 00000001 ? leir1 [r/w] 000-0000 100214 h rtec1 [r] 00000000 00000000 btr1 [r/w] -1111111 11111111 100218 h ider1 [r/w] xxxxxxxx xxxxxxxx trtrr1 [r/w] 00000000 00000000 10021c h rfwtr1 [r/w] xxxxxxxx xxxxxxxx tier1 [r/w] 00000000 00000000 100220 h amsr1 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 100224 h amr01 [r/w] xxxxxxxx xxxxxxxx xxxxx - - - xxxxxxxx 100228 h amr11 [r/w] xxxxxxxx xxxxxxxx xxxxx - - - xxxxxxxx 10022c h to 100248 h general purpose ram [r/w] 10024c h idr01 [r/w] xxxxxxxx xxxxxxxx xxxxx - - - xxxxxxxx 100250 h idr11 [r/w] xxxxxxxx xxxxxxxx xxxxx - - - xxxxxxxx 100254 h idr21[r/w] xxxxxxxx xxxxxxxx xxxxx - - - xxxxxxxx 100258 h idr31 [r/w] xxxxxxxx xxxxxxxx xxxxx - - - xxxxxxxx- 10025c h idr41 [r/w] xxxxxxxx xxxxxxxx xxxxx - - - xxxxxxxx 100260 h idr51 [r/w] xxxxxxxx xxxxxxxx xxxxx - - - xxxxxxxx 100264 h idr61 [r/w] xxxxxxxx xxxxxxxx xxxxx - - - xxxxxxxx
mb91360g series 65 (continued) address register block + + + + 0 + + + + 1 + + + + 2 + + + + 3 100268 h idr71 [r/w] xxxxxxxx xxxxxxxx xxxxx - - - xxxxxxxx can 1 10026c h idr81 [r/w] xxxxxxxx xxxxxxxx xxxxx - - - xxxxxxxx 100270 h idr91 [r/w] xxxxxxxx xxxxxxxx xxxxx - - - xxxxxxxx 100274 h idr101 [r/w] xxxxxxxx xxxxxxxx xxxxx - - - xxxxxxxx 100278 h idr111 [r/w] xxxxxxxx xxxxxxxx xxxxx - - - xxxxxxxx 10027c h idr121 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxx - - - 100280 h idr131 [r/w] xxxxxxxx xxxxxxxx xxxxx - - - xxxxxxxx 100284 h idr141 [r/w] xxxxxxxx xxxxxxxx xxxxx - - - xxxxxxxx 100288 h idr151 [r/w] xxxxxxxx xxxxxxxx xxxxx - - - xxxxxxxx 10028c h dlcr01 [r/w] - - - - - - - - - - - - xxxx dlcr11 [r/w] - - - - - - - - - - - - xxxx 100290 h dlcr21 [r/w] - - - - - - - - - - - - xxxx dlcr31 [r/w] - - - - - - - - - - - - xxxx 100294 h dlcr41 [r/w] - - - - - - - - - - - - xxxx dlcr51 [r/w] - - - - - - - - - - - - xxxx 100298 h dlcr61 [r/w] - - - - - - - - - - - - xxxx dlcr71 [r/w] - - - - - - - - - - - - xxxx 10029c h dlcr81[r/w] - - - - - - - - - - - - xxxx dlcr91 [r/w] - - - - - - - - - - - - xxxx 1002a0 h dlcr101 [r/w] - - - - - - - - - - - - xxxx dlcr111 [r/w] - - - - - - - - - - - - xxxx 1002a4 h dlcr121 [r/w] - - - - - - - - - - - - xxxx dlcr131 [r/w] - - - - - - - - - - - - xxxx 1002a8 h dlcr141 [r/w] - - - - - - - - - - - - xxxx dlcr151 [r/w] - - - - - - - - - - - - xxxx 1002ac h dtr01 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx
mb91360g series 66 (continued) address register block + + + + 0 + + + + 1 + + + + 2 + + + + 3 1002b4 h dtr11 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx can 1 1002bc h dtr21 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 1002c4 h dtr31 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 1002cc h dtr41 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 1002d4 h dtr51 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 1002dc h dtr61 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 1002e4 h dtr71 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 1002ec h dtr81 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 1002f4 h dtr91 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 1002fc h dtr101 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 100304 h dtr111 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 10030c h dtr121 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 100314 h dtr131 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 10031c h dtr141 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx
mb91360g series 67 (continued) address register block + + + + 0 + + + + 1 + + + + 2 + + + + 3 100324 h dtr151 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx can 1 10032c h creg1 [r/w] 00000000 00000110 ? 100400 h bvalr2 [r/w] 00000000 00000000 treqr2 [r/w] 00000000 00000000 can 2 remark : address range for can 0 to can 3 depends on chip select range. mentioned addresses are default values, determined by boot rom contents. 100404 h tcanr2 [w] 00000000 00000000 tcr2 [r/w] 00000000 00000000 100408 h rcr2 [r/w] 00000000 00000000 rrtrr1 [r/w] 00000000 00000000 10040c h rovrr2 [r/w] 00000000 00000000 rier2 [r/w] 00000000 00000000 100410 h csr2 [r/w, r] 00000000 00000001 ? leir2 [r/w] 000-0000 100414 h rtec2 [r] 00000000 00000000 btr2 [r/w] -1111111 11111111 100418 h ider2 [r/w] xxxxxxxx xxxxxxxx trtrr2 [r/w] 00000000 00000000 10041c h rfwtr2 [r/w] xxxxxxxx xxxxxxxx tier2 [r/w] 00000000 00000000 100420 h amsr2 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 100424 h amr02 [r/w] xxxxxxxx xxxxxxxx xxxxx - - - xxxxxxxx 100428 h amr12 [r/w] xxxxxxxx xxxxxxxx xxxxx - - - xxxxxxxx 10042c h to 100448 h general purpose ram [r/w] 10044c h idr02 [r/w] xxxxxxxx xxxxxxxx xxxxx - - - xxxxxxxx 100450 h idr12 [r/w] xxxxxxxx xxxxxxxx xxxxx - - - xxxxxxxx 100454 h idr22[r/w] xxxxxxxx xxxxxxxx xxxxx - - - xxxxxxxx 100458 h idr32 [r/w] xxxxxxxx xxxxxxxx xxxxx - - - xxxxxxxx- 10045c h idr42 [r/w] xxxxxxxx xxxxxxxx xxxxx - - - xxxxxxxx
mb91360g series 68 (continued) address register block + + + + 0 + + + + 1 + + + + 2 + + + + 3 100460 h idr52 [r/w] xxxxxxxx xxxxxxxx xxxxx - - - xxxxxxxx can 2 100464 h idr62 [r/w] xxxxxxxx xxxxxxxx xxxxx - - - xxxxxxxx 100468 h idr72 [r/w] xxxxxxxx xxxxxxxx xxxxx - - - xxxxxxxx 10046c h idr82 [r/w] xxxxxxxx xxxxxxxx xxxxx - - - xxxxxxxx 100470 h idr92 [r/w] xxxxxxxx xxxxxxxx xxxxx - - - xxxxxxxx 100474 h idr102 [r/w] xxxxxxxx xxxxxxxx xxxxx - - - xxxxxxxx 100478 h idr112 [r/w] xxxxxxxx xxxxxxxx xxxxx - - - xxxxxxxx 10047c h idr122 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxx - - - 100480 h idr132 [r/w] xxxxxxxx xxxxxxxx xxxxx - - - xxxxxxxx 100484 h idr142 [r/w] xxxxxxxx xxxxxxxx xxxxx - - - xxxxxxxx 100488 h idr152 [r/w] xxxxxxxx xxxxxxxx xxxxx - - - xxxxxxxx 10048c h dlcr02 [r/w] - - - - - - - - - - - - xxxx dlcr12 [r/w] - - - - - - - - - - - - xxxx 100490 h dlcr22 [r/w] - - - - - - - - - - - - xxxx dlcr32 [r/w] - - - - - - - - - - - - xxxx 100494 h dlcr42 [r/w] - - - - - - - - - - - - xxxx dlcr52 [r/w] - - - - - - - - - - - - xxxx 100498 h dlcr62 [r/w] - - - - - - - - - - - - xxxx dlcr72 [r/w] - - - - - - - - - - - - xxxx 10049c h dlcr82[r/w] - - - - - - - - - - - - xxxx dlcr92 [r/w] - - - - - - - - - - - - xxxx 1004a0 h dlcr102 [r/w] - - - - - - - - - - - - xxxx dlcr112 [r/w] - - - - - - - - - - - - xxxx 1004a4 h dlcr122 [r/w] - - - - - - - - - - - - xxxx dlcr132 [r/w] - - - - - - - - - - - - xxxx 1004a8 h dlcr142 [r/w] - - - - - - - - - - - - xxxx dlcr152 [r/w] - - - - - - - - - - - - xxxx
mb91360g series 69 (continued) address register block + + + + 0 + + + + 1 + + + + 2 + + + + 3 1004ac h dtr02 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx can 2 1004b4 h dtr12 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 1004bc h dtr22 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 1004c4 h dtr32 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 1004cc h dtr42 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 1004d4 h dtr52 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 1004dc h dtr62 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 1004e4 h dtr72 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 1004ec h dtr82 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 1004f4 h dtr92 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 1004fc h dtr102 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 100504 h dtr112 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 10050c h dtr122 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 100514 h dtr132 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx
mb91360g series 70 (continued) address register block + + + + 0 + + + + 1 + + + + 2 + + + + 3 10051c h dtr142 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx can 2 100524 h dtr152 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 10052c h creg2 [r/w] 00000000 00000110 ? 100600 h bvalr3 [r/w] 00000000 00000000 treqr3 [r/w] 00000000 00000000 can 3 remark : address range for can 0 to can 3 depends on chip select range. mentioned addresses are default values, determined by boot rom contents. 100604 h tcanr3 [w] 00000000 00000000 tcr3 [r/w] 00000000 00000000 100608 h rcr3 [r/w] 00000000 00000000 rrtrr31 [r/w] 00000000 00000000 10060c h rovrr3 [r/w] 00000000 00000000 rier3 [r/w] 00000000 00000000 100610 h csr3 [r/w, r] 00000000 00000001 ? leir3 [r/w] 000-0000 100614 h rtec3 [r] 00000000 00000000 btr3 [r/w] -1111111 11111111 100618 h ider3 [r/w] xxxxxxxx xxxxxxxx trtrr3 [r/w] 00000000 00000000 10061c h rfwtr3 [r/w] xxxxxxxx xxxxxxxx tier3 [r/w] 00000000 00000000 100620 h amsr3 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 100624 h amr03 [r/w] xxxxxxxx xxxxxxxx xxxxx - - - xxxxxxxx 100628 h amr13 [r/w] xxxxxxxx xxxxxxxx xxxxx - - - xxxxxxxx 10062c h to 100648 h general purpose ram [r/w] 10064c h idr03 [r/w] xxxxxxxx xxxxxxxx xxxxx - - - xxxxxxxx 100650 h idr13 [r/w] xxxxxxxx xxxxxxxx xxxxx - - - xxxxxxxx 100654 h idr23[r/w] xxxxxxxx xxxxxxxx xxxxx - - - xxxxxxxx 100658 h idr33 [r/w] xxxxxxxx xxxxxxxx xxxxx - - - xxxxxxxx-
mb91360g series 71 (continued) address register block + + + + 0 + + + + 1 + + + + 2 + + + + 3 10065c h idr43 [r/w] xxxxxxxx xxxxxxxx xxxxx - - - xxxxxxxx can 3 100660 h idr53 [r/w] xxxxxxxx xxxxxxxx xxxxx - - - xxxxxxxx 100664 h idr63 [r/w] xxxxxxxx xxxxxxxx xxxxx - - - xxxxxxxx 100668 h idr73 [r/w] xxxxxxxx xxxxxxxx xxxxx - - - xxxxxxxx 10066c h idr83 [r/w] xxxxxxxx xxxxxxxx xxxxx - - - xxxxxxxx 100670 h idr93 [r/w] xxxxxxxx xxxxxxxx xxxxx - - - xxxxxxxx 100674 h idr103 [r/w] xxxxxxxx xxxxxxxx xxxxx - - - xxxxxxxx 100678 h idr113 [r/w] xxxxxxxx xxxxxxxx xxxxx - - - xxxxxxxx 10067c h idr123 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxx - - - 100680 h idr133 [r/w] xxxxxxxx xxxxxxxx xxxxx - - - xxxxxxxx 100684 h idr143 [r/w] xxxxxxxx xxxxxxxx xxxxx - - - xxxxxxxx 100688 h idr153 [r/w] xxxxxxxx xxxxxxxx xxxxx - - - xxxxxxxx 10068c h dlcr032 [r/w] - - - - - - - - - - - - xxxx dlcr13 [r/w] - - - - - - - - - - - - xxxx 100690 h dlcr232 [r/w] - - - - - - - - - - - - xxxx dlcr33 [r/w] - - - - - - - - - - - - xxxx 100694 h dlcr43 [r/w] - - - - - - - - - - - - xxxx dlcr53 [r/w] - - - - - - - - - - - - xxxx 100698 h dlcr63 [r/w] - - - - - - - - - - - - xxxx dlcr733 [r/w] - - - - - - - - - - - - xxxx 10069c h dlcr83[r/w] - - - - - - - - - - - - xxxx dlcr93 [r/w] - - - - - - - - - - - - xxxx 1006a0 h dlcr103 [r/w] - - - - - - - - - - - - xxxx dlcr113 [r/w] - - - - - - - - - - - - xxxx 1006a4 h dlcr123 [r/w] - - - - - - - - - - - - xxxx dlcr133 [r/w] - - - - - - - - - - - - xxxx 1006a8 h dlcr143 [r/w] - - - - - - - - - - - - xxxx dlcr153 [r/w] - - - - - - - - - - - - xxxx
mb91360g series 72 (continued) address register block + + + + 0 + + + + 1 + + + + 2 + + + + 3 1006ac h dtr03 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx can 3 1006b4 h dtr13 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 1006bc h dtr23 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 1006c4 h dtr33 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 1006cc h dtr43 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 1006d4 h dtr53 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 1006dc h dtr63 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 1006e4 h dtr73 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 1006ec h dtr83 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 1006f4 h dtr93 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 1006fc h dtr103 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 100704 h dtr113 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 10070c h dtr123 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 100714 h dtr133 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx
mb91360g series 73 (continued) address register block + + + + 0 + + + + 1 + + + + 2 + + + + 3 10071c h dtr143 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx can 3 100724 h dtr153 [r/w] xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 10072c h creg3 [r/w] 00000000 00000110 ?
mb91360g series 74 n interrupt causes, interrupt vectors, and interrupt control register (continued) interrupt interrupt number interrupt level *1 interrupt vector *2 rn decimal hexa- decimal setting register register address offset default vector address reset 0 00 ?? 0x3fc 0x000ffffc ? mode vector 1 01 ?? 0x3f8 0x000ffff8 ? system reserved 2 02 ?? 0x3f4 0x000ffff4 ? system reserved 3 03 ?? 0x3f0 0x000ffff0 ? system reserved 4 04 ?? 0x3ec 0x000fffec ? system reserved 5 05 ?? 0x3e8 0x000fffe8 ? system reserved 6 06 ?? 0x3e4 0x000fffe4 ? co-processor fault trap *4 707 ?? 0x3e0 0x000fffe0 ? co-processor error trap *4 808 ?? 0x3dc 0x000fffdc ? inte instruction *4 909 ?? 0x3d8 0x000fffd8 ? instruction break exception *4 10 0a ?? 0x3d4 0x000fffd4 ? operand break trap *4 11 0b ?? 0x3d0 0x000fffd0 ? step trace trap *4 12 0c ?? 0x3cc 0x000fffcc ? nmi interrupt (tool) *4 13 0d ?? 0x3c8 0x000fffc8 ? undefined instruction exception 14 0e ?? 0x3c4 0x000fffc4 ? nmi request 15 0f f h fixed 0x3c0 0x000fffc0 ? external interrupt 0 16 10 icr00 0x440 0x3bc 0x000fffbc 4 external interrupt 1 17 11 icr01 0x441 0x3b8 0x000fffb8 5 external interrupt 2 18 12 icr02 0x442 0x3b4 0x000fffb4 8 external interrupt 3 19 13 icr03 0x443 0x3b0 0x000fffb0 9 external interrupt 4 20 14 icr04 0x444 0x3ac 0x000fffac ? external interrupt 5 21 15 icr05 0x445 0x3a8 0x000fffa8 ? external interrupt 6 22 16 icr06 0x446 0x3a4 0x000fffa4 ? external interrupt 7 23 17 icr07 0x447 0x3a0 0x000fffa0 ? reload timer 0 24 18 icr08 0x448 0x39c 0x000fff9c 6 reload timer 1 25 19 icr09 0x449 0x398 0x000fff98 7 reload timer 2 26 1a icr10 0x44a 0x394 0x000fff94 ? can 0 rx 27 1b icr11 0x44b 0x390 0x000fff90 ? can 0 tx/ns 28 1c icr12 0x44c 0x38c 0x000fff8c ? can 1 rx 29 1d icr13 0x44d 0x388 0x000fff88 ? can 1 tx/ns 30 1e icr14 0x44e 0x384 0x000fff84 ?
mb91360g series 75 (continued) interrupt interrupt number interrupt level *1 interrupt vector *2 rn decimal hexa- decimal setting register register address offset default vector address can 2 rx 31 1f icr15 0x44f 0x380 0x000fff80 ? can 2 tx/ns 32 20 icr16 0x450 0x37c 0x000fff7c ? can 3 rx *5 33 21 icr17 0x451 0x378 0x000fff78 ? can 3 tx/ns *5 34 22 icr18 0x452 0x374 0x000fff74 ? ppg 0/1 35 23 icr19 0x453 0x370 0x000fff70 ? ppg 2/3 36 24 icr20 0x454 0x36c 0x000fff6c ? ppg 4/5 37 25 icr21 0x455 0x368 0x000fff68 ? ppg 6/7 38 26 icr22 0x456 0x364 0x000fff64 ? reload timer 3 39 27 icr23 0x457 0x360 0x000fff60 ? reload timer 4 40 28 icr24 0x458 0x35c 0x000fff5c ? reload timer 5 41 29 icr25 0x459 0x358 0x000fff58 ? icu 0/1 42 2a icr26 0x45a 0x354 0x000fff54 ? ocu 0/1 43 2b icr27 0x45b 0x350 0x000fff50 ? icu 2/3 44 2c icr28 0x45c 0x34c 0x000fff4c ? ocu 2/3 45 2d icr29 0x45d 0x348 0x000fff48 ? adc 46 2e icr30 0x45e 0x344 0x000fff44 14 timebase overflow 47 2f icr31 0x45f 0x340 0x000fff40 ? free running counter 0 48 30 icr32 0x460 0x33c 0x000fff3c ? free running counter 1 49 31 icr33 0x461 0x338 0x000fff38 ? sio 0 *6 50 32 icr34 0x462 0x334 0x000fff34 12 sio 1 *6 51 33 icr35 0x463 0x330 0x000fff30 15 sound generator 52 34 icr36 0x464 0x32c 0x000fff2c ? uart 0 rx 53 35 icr37 0x465 0x328 0x000fff28 0 uart 0 tx 54 36 icr38 0x466 0x324 0x000fff24 1 uart 1 rx 55 37 icr39 0x467 0x320 0x000fff20 2 uart 1 tx 56 38 icr40 0x468 0x31c 0x000fff1c 3 uart 2 rx 57 39 icr41 0x469 0x318 0x000fff18 10 uart 2 tx 58 3a icr42 0x46a 0x314 0x000fff14 11 i 2 c *7 59 3b icr43 0x46b 0x310 0x000fff10 13 alarm comparator 60 3c icr44 0x46c 0x30c 0x000fff0c ? rtc (watchtimer) / calibration unit 61 3d icr45 0x46d 0x308 0x000fff08 ? dma 62 3e icr46 0x46e 0x304 0x000fff04 ?
mb91360g series 76 (continued) *1 : the icrs are located in the interrupt controller and set the interrupt level for each interrupt request. an icr is provided for each interrupt request. *2 : the vector address for each eit (exception, interrupt or trap) is calculated by adding the listed offset to the table base register value (tbr) . the tbr specifies the top of the eit vector table. the addresses listed in the table are for the default tbr value (0x000ffc00) . the tbr is initialized to this value by a reset.after execution of the internal boot rom tbr is set to 0x00ffc00. *3 : used by realos *4 : system reserved *5 : only available on mb91fv360ga *6 : dma to/from sio only implemented on f369ga. *7 : dma to/from i 2 c is not implemented on mb91f362ga. remarks : the 1-kbyte area from the address specified in trb is the eit vector area. each vector consists of four bytes. the following formula shows the relationship between the vector number and vector address. vector = tbr + vctofs = tbr + (3fc h - 4 vct) vctadr : vector address vctofs : vector offset vct : vector number interrupt interrupt number interrupt level *1 interrupt vector *2 rn decimal hexa- decimal setting register register address offset default vector address delayed interrupt activation bit 63 3f icr47 0x46f 0x300 0x000fff00 ? ? system reserved *3 64 40 ?? 0x2fc 0x000ffefc ? system reserved *3 65 41 ?? 0x2f8 0x000ffef8 ? security vector 66 42 ?? 0x2f4 0x000ffef4 ? system reserved 67 43 (icr51) 0x473 0x2f0 0x000ffef0 ? system reserved 68 44 (icr52) 0x474 0x2ec 0x000ffeec ? system reserved 69 45 (icr53) 0x475 0x2e8 0x000ffee8 ? system reserved 70 46 (icr54) 0x476 0x2e4 0x000ffee4 ? system reserved 71 47 (icr55) 0x477 0x2e0 0x000ffee0 ? system reserved 72 48 (icr56) 0x478 0x2dc 0x000ffedc ? system reserved 73 49 (icr57) 0x479 0x2d8 0x000ffed8 ? system reserved 74 4a (icr58) 0x47a 0x2d4 0x000ffed4 ? system reserved 75 4b (icr59) 0x47b 0x2d0 0x000ffed0 ? system reserved 76 4c (icr60) 0x47c 0x2cc 0x000ffecc ? system reserved 77 4d (icr61) 0x47d 0x2c8 0x000ffec8 ? system reserved 78 4e (icr62) 0x47e 0x2c4 0x000ffec4 ? system reserved 79 4f (icr63) 0x47f 0x2c0 0x000ffec0 ? used by the int instruction. 80 to 255 50 to ff ?? 0x2bc to 0x000 0x000ffebc to 0x000ffc00 ? ? ?
mb91360g series 77 n peripheral resources 1. instruction cache this section describes the instruction cache memory included in FR50 family members and it operation. this only applies to mb91fv360ga. (1) general description the instruction cache is temporary memory. when an external low-speed memory accesses an instruction code, the instruction cache stores the single-accessed code to increase the second and subsequent access speeds.setting this memory to the ram mode enables software to directly read and write instruction cache data ram and tag ram. (2) main body structure instruction cache structure ? fr basic instruction length : 2 bytes ? block arrangement system : 2-way set associative system ? block one way consists of 128 blocks. one block consists of 16 bytes ( = 4 sub-blocks) . one sub-block consists of 4 bytes ( = 1 bus access unit) . 4 bytes 4 bytes 4 bytes 4 bytes 4 bytes i3 i2 i1 i0 way 1 way 2 cache tag sub-block 3 sub-block 2 sub-block 1 sub-block 0 block 0 sub-block 3 sub-block 2 sub-block 1 sub-block 0 block 127 block 0 block 127 sub-block 3 sub-block 2 sub-block 1 sub-block 0 sub-block 3 sub-block 2 sub-block 1 sub-block 0 cache tag cache tag cache tag 128 blocks 128 blocks
mb91360g series 78 instruction cache tag 07 06 05 04 03 02 01 00 sbv2 sbv3 abv1 sbv0 tagv reserved lru etlk 31 way 1 09 08 address tag reserved tag valid sub-block valid lru entry lock 07 06 05 04 03 02 01 00 sbv2 sbv3 abv1 sbv0 tagv reserved etlk 31 way 2 09 08 address tag reserved tag valid sub-block valid entry lock
mb91360g series 79 (3) control register structure irbs [bits 15 to 12] these bits are used to set the base address of cache ram at access in the ram mode. align cache ram in units of 4 k bytes. these bits are initialized by init. the initial value is the 00012000 h address. the ichcr (i-cache control register) controls the instruction cache operations. writing to the ichcr does not affect caching of instructions fetched within three subsequent cycles. irbs (32 bits) initial value address : 00000300 h 00000000 b initial value 00000001 b icr26 initial value address : 00000302 h 0010 - - - - b initial value - - - - - - - - b isize (8 bits) initial value 00000307 h - - - - - - 11 b ichcr (8 bits) initial value 000003e7 h 0 - 000000 b rr rrrr r 31 30 29 28 27 26 25 24 0 r 0 0 00000 rr rrrr r 23 22 21 20 19 18 17 16 0 r 0 0 00001 r/w r/w r/w ???? 15 14 13 12 11 10 9 8 irbs r/w irbs irbs irbs ???? ?? ???? ? 76543210 ? ? ? ? ????? ?? ??? r/w r/w 76543210 ? ? ????? size1 size0 ? r/w r/w r/w r/w r/w r/w 76543210 ? r/w ram gblk alfl eolk elkr flsh enab
mb91360g series 80 2. boot rom the boot rom is a fixed start-up routine which is located at ff000 (reset entry) and will therefore be executed after every rst or init. the purpose of this rom is to configure the device after a reset and to provide a simple serial bootloader for programming the embedded flash memories. the boot rom contains three logical parts : (1) chip initializations immediately after each reset, the following settings will be made : cs0 : 2000002fffff, 32 bit bus, 1 wait-state (default external access) cs7 : 10000010ffff, 16 bit bus, 1 wait-state (can) in addition, the table-base register will be initialized to 1ffc00 (f361ga only) and the synchronous reset (see tbcr) will be enabled. (2) check for bootcondition after the chip initialization, the security-vector will be checked (vector #66) . the purpose of this feature is to disable the bootstraploader due to security reasons. the rsrr (reset cause register) will be read and saved. if no power-on reset (external initx input, rsrr = 0x80) is indicated, a branch to the user application will be initiated (branch to 1f4000) . if initx was detected and the security-vector check okay, the following conditions must be met in order to start the bootstraploader : within a certain time, the start-up character v must be received via uart0 (9600, 8n1) . the time-out is set to 200 ms. (3) bootstraploader if the bootcondition was met, an acknowledge character f will be transmitted via uart0 to indicate that the bootloader is ready to accept commands. 4 different commands are possible : receive and write to a specified memory block dump the contents of a specified memory block initiate a call to a certain location re-dump a calculated checksum for verification (4) configuration register (f362mode register f362md) this register is used to control which pins of the external bus interface are active, where the pins for the external dma channel are located and which i 2 c module is used. address 00001fe h access initial value r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 asymclkt hiz_d_a hiz_eclk hiz_d_23_16 hiz_d_15_0 dmaswp iicsel adrswap r/w 0
mb91360g series 81 3. clock modulator an important property of mcus and other electronic devices is their electromagnetic compatibility - emc. besides a low susceptibility against external interferences, a low radiated emission is desired to avoid interference of adjacent devices. particularly the system clock and derived signals such as data- and address busses contribute significantly to the radiated emission. the purpose of the clock modulator is to spread the energy of these signals over a wide range of frequencies and thus reducing the amplitudes of the fundamental and harmonic frequencies. with the use of an advanced frequency modulation algorithm, the fujitsu built in clock modulator can achieve an attenuation of up to 20-25 db compared to non modulated clock operation. since the modulator is highly configurable, it can be optimally adjusted to the actual application in order to achieve minimal electromagnetic interference. by default, the modulator is disabled and the mcu is running with unmodulated clock. if you plan to use this feature, please contact fujitsu.
mb91360g series 82 4. i/o ports the i / o port registers consist of the port data registers ( pdr ) , the data direction registers ( ddr ) and the port function registers ( pfr ) . the bits in pdrs correspond to the bits in ddrs and pfrs. similarly, the register bits correspond to the port pins. the port data registers contain the port i/o data and the data direction registers specify whether the correspond- ing bits (pins) are inputs or outputs. bits set to 0 are inputs and bits set to 1 are outputs. the port function registers specify whether the port is used as peripheral port or as i/o port. usually bits set to 0 mean i/o port and bits set to 1 mean functional port. in case of analog peripherals there is additional circuitry to ensure that the digital logic is not disturbed by the analog signals. if the analog input function e.g. adc is enabled the digital input is fixed to 0. ? input mode (ddr = 0) pdr read : reads the level on the corresponding external pin. pdr write : writes the pdr setting value. ? output mode (ddr = 1) pdr read : reads the pdr value. pdr write : outputs the pdr value to the corresponding external pins.
mb91360g series 83 (1) register configuration port data register (continued) pdr7 initial value access address : 00000007 h 1111xxxx b r/w pdr8 initial value access address : 00000008 h xxxxxxxx b r/w pdr9 initial value access address : 00000009 h xxxxxxx1 b r/w pdrb initial value access address : 0000000b h xxxxxxxx b r/w pdrg initial value access address : 00000010 h xxxxxxxx b r/w pdrh initial value access address : 00000011 h xxxxxxxx b r/w pdri initial value access address : 00000012 h x - - - x - - - b r/w pdrj initial value access address : 00000013 h xxxxxxxx b r/w pdrk initial value access address : 00000014 h xxxxxxxx b r/w pdrl initial value access address : 00000015 h xxxxxxxx b r/w pdrm initial value access address : 00000016 h - - - - xxxx b r/w pdrn initial value access address : 00000017 h - -xxxxxx b r/w pdro initial value access address : 00000018 h xxxxxxxx b r/w 76543210 p76 p77 p75 p74 p73 p72 p71 p70 76543210 p86 p87 p85 p84 p83 p82 p81 p80 76543210 p96 p97 p95 p94 p93 p92 p91 p90 76543210 pb6 pb7 pb5 pb4 pb3 pb2 pb1 pb0 76543210 pg6 pg7 pg5 pg4 pg3 pg2 pg1 pg0 76543210 pg6 pg7 pg5 pg4 pg3 pg2 pg1 pg0 76543210 ph6 ph7 ph5 ph4 ph3 ph2 ph1 ph0 76543210 ?? ? pi3 ??? p17 76543210 pj6 pj7 pj5 pj4 pj3 pj2 pj1 pj0 76543210 pk6 pk7 pk5 pk4 pk3 pk2 pk1 pk0 76543210 pl6 pl7 pl5 pl4 pl3 pl2 pl1 pl0 76543210 ? ? pm3 pm2 pm1 pm0 ? ? 76543210 ? ? pn5 pn4 pn3 pn2 pn1 pn0 76543210 po6 po7 po5 po4 po3 po2 po1 po0
mb91360g series 84 (continued) pdrp initial value access address : 00000019 h xxxxxxxx b r/w pdrq initial value access address : 0000001a h --xxxxxx b r/w pdrr initial value access address : 0000001b h xxxxxxxx b r/w pdrs initial value access address : 0000001c h xxxxxxxx b r/w 76543210 pp6 pp7 pp5 pp4 pp3 pp2 pp1 pp0 76543210 ? ? pq5 pq4 pq3 pq2 pq1 pq0 76543210 pr6 pr7 pr5 pr4 pr3 pr2 pr1 pr0 76543210 ps6 ps7 ps5 ps4 ps3 ps2 ps1 ps0
mb91360g series 85 data directon register (continued) ddr7 initial value access address : 00000607 h 00000000 b r/w ddr8 initial value access address : 00000608 h 00000000 b r/w ddr9 initial value access address : 00000609 h 00000000 b r/w ddrb initial value access address : 0000600b h 00000000 b r/w ddrg initial value access address : 00000400 h 00000000 b r/w ddrh initial value access address : 00000401 h 00000000 b r/w ddri initial value access address : 00000402 h - - - - 0 - - - b r/w ddrj initial value access address : 00000403 h 00000000 b r/w ddrk initial value access address : 00000404 h 00000000 b r/w ddrl initial value access address : 00000405 h 00000000 b r/w ddrm initial value access address : 00000406 h - - - - 0000 b r/w ddrn initial value access address : 00000407 h - -000000 b r/w ddro initial value access address : 00000408 h 00000000 b r/w 76543210 p76 p77 p75 p74 p73 p72 p71 p70 76543210 p86 p87 p85 p84 p83 p82 p81 p80 76543210 p96 p97 p95 p94 p93 p92 p91 p90 76543210 pb6 pb7 pb5 pb4 pb3 pb2 pb1 pb0 76543210 pg6 pg7 pg5 pg4 pg3 pg2 pg1 pg0 76543210 pg6 pg7 pg5 pg4 pg3 pg2 pg1 pg0 76543210 ph6 ph7 ph5 ph4 ph3 ph2 ph1 ph0 76543210 ?? ? pi3 ??? ? 76543210 pj6 pj7 pj5 pj4 pj3 pj2 pj1 pj0 76543210 pk6 pk7 pk5 pk4 pk3 pk2 pk1 pk0 76543210 pl6 pl7 pl5 pl4 pl3 pl2 pl1 pl0 76543210 ? ? pm3 pm2 pm1 pm0 ? ? 76543210 ? ? pn5 pn4 pn3 pn2 pn1 pn0 76543210 po6 po7 po5 po4 po3 po2 po1 po0
mb91360g series 86 (continued) ddrp initial value access address : 00000409 h 00000000 b r/w ddrq initial value access address : 0000040a h --000000 b r/w ddrr initial value access address : 0000040b h 00000000 b r/w ddrs initial value access address : 0000040c h 00000000 b r/w 76543210 pp6 pp7 pp5 pp4 pp3 pp2 pp1 pp0 76543210 ? ? pq5 pq4 pq3 pq2 pq1 pq0 76543210 pr6 pr7 pr5 pr4 pr3 pr2 pr1 pr0 76543210 ps6 ps7 ps5 ps4 ps3 ps2 ps1 ps0
mb91360g series 87 port function registers (pfr) (continued) pfr7 initial value access address : 00000617 h 00001111 b r/w pfr8 initial value access address : 00000618 h 111110 - - b r/w pfr9 initial value access address : 00000619 h 11110101 b r/w pfrb initial value access address : 0000061b h 00000000 b r/w pfr27 initial value access address : 00000627 h 1111 - 00 - b r/w pfrg initial value access address : 00000410 h 00000000 b r/w pfrh initial value access address : 00000411 h 00000000 b r/w pfri initial value access address : 00000412 h - - - - 0 - - - b r/w pfrj initial value access address : 00000413 h 00000000 b r/w pfrk initial value access address : 00000414 h 00000000 b r/w pfrl initial value access address : 00000415 h 00000000 b r/w pfrm initial value access address : 00000416 h - - - - 0000 b r/w pfrn initial value access address : 00000417 h - - 000000 b r/w 76543210 p76 p77 p75 p74 p73 p72 p71 p70 76543210 p86 p87 p85 p84 p83 p82 ?? 76543210 p96 p97 p95 p94 p93 p92 p91 p90 76543210 pb6 pb7 pb5 pb4 pb3 pb2 pb1 pb0 76543210 p276 p277 p275 p274 p273 p272 p271 p270 76543210 pg6 pg7 pg5 pg4 pg3 pg2 pg1 pg0 76543210 ph6 ph7 ph5 ph4 ph3 ph2 ph1 ph0 76543210 ? ??? pi3 ??? 76543210 pj6 pj7 pj5 pj4 pj3 pj2 pj1 pj0 76543210 pk6 pk7 pk5 pk4 pk3 pk2 pk1 pk0 76543210 pl6 pl7 pl5 pl4 pl3 pl2 pl1 pl0 76543210 ? ??? pm3 pm2 pm1 pm0 76543210 ? ? pn5 pn4 pn3 pn2 pn1 pn0
mb91360g series 88 (continued) pfro initial value access address : 00000418 h 00000000 b r/w pfrp initial value access address : 00000419 h 00000000 b r/w pfrq initial value access address : 0000041a h - - 000000 b r/w pfrr initial value access address : 0000041b h 00000000 b r/w pfrs initial value access address : 0000041c h 00000000 b r/w 76543210 po6 po7 po5 po4 po3 po2 po1 po0 76543210 pp6 pp7 pp5 pp4 pp3 pp2 pp1 pp0 76543210 ? ? pq5 pq4 pq3 pq2 pq1 pq0 76543210 pr6 pr7 pr5 pr4 pr3 pr2 pr1 pr0 76543210 ps6 ps7 ps5 ps4 ps3 ps2 ps1 ps0
mb91360g series 89 5. dma controller ( dmac ) the dmac module is used to implement direct memory access (dma) transfer in FR50 series devices. in a dma transfer controlled by this module, various types of data can be transferred at high speed without involving the cpu, thus increasing system performance. (1) hardware configuration the following are the main components of the dmac module : ? five independent dma channels ? 5-channel independent access control circuit ? 32-bit address registers (reload can be specified : two registers for each channel.) ? 16-bit transfer count registers (reload can be specified : one register for each channel.) ? 4-bit block count registers (one register for each channel) ? external transfer request input pins dreq0, dreq1, and dreq2 (only channels 0, 1, and 2) ? external transfer request acceptance output pins dack0, dack1, and dack2 (only channels 0, 1, and 2) ? dma termination output pins deop0, deop1, and deop2 (only channels 0, 1, and 2) ? two-cycle transfer (2) main functions the following are the main functions of data transfer performed by the module : ? independent data transfer in multiple channels is enabled (5 channels) . a : priority (channel 0 > channel 1 > channel 2 > channel 3 > channel 4) b : priority can be alternated between channel 0 and channel 1. c : dmac start cause external-only pin input (edge detection/level detection channels 0 to 2 only) internal peripheral request (interrupt request is shared, including external interrupts) software request (register write) d : transfer mode demand transfer, burst transfer, step transfer, block transfer addressing mode 32-bit full address specification (increase, decrease, fixed) (an address increment/decrement size of - 255 to + 255 can be specified.) data types of byte, halfword, and word lengths single-shot/reload selectable
mb91360g series 90 (3) registers configuration channel 0 control/status register a channel 0 control/status register b channel 1 control/status register a channel 1 control/status register b channel 2 control/status register a channel 2 control/status register b channel 3 control/status register a channel 3 control/status register b channel 4 control/status register a channel 4 control/status register b overall control register channel 0 transfer source address register channel 0 transfer destination address register channel 1 transfer source address register channel 1 transfer destination address register channel 2 transfer source address register channel 2 transfer destination address register channel 3 transfer source address register channel 3 transfer destination address register channel 4 transfer source address register channel 4 transfer destination address register 0000200 h 0000204 h 0000208 h 000020c h 0000210 h 0000214 h 0000218 h 000021c h 0000220 h 0000224 h 0000240 h 0001000 h 0001004 h 0001008 h 000100c h 0001010 h 0001014 h 0001018 h 000101c h 0001020 h 0001028 h dmaca0 dmacb0 dmaca1 dmacb1 dmaca2 dmacb2 dmaca3 dmacb3 dmaca4 dmacb4 dmacr dmasa0 dmada0 dmasa1 dmada1 dmasa2 dmada2 dmasa3 dmada3 dmasa4 dmada4
mb91360g series 91 (4) block diagram read write read/write control to bus controller dma trnasfer request to bus controller ddno access address write-back write-back selector selector selector counter buffer counter buffer address counter bus control section blk register ddno register dma control dtcr priority circuit status transition circuit counter dma start cause selection circuit and request acceptance control write back buffer selector counter buffer selector dtc 2-step register dss [3:0] peripheral start request/stop external pin start request/stop input input to transfer controller clear peripheral interrupt bus control section erir, edir type, mod, ws irq [4:0] mclreq x-bus dadm, dasz [7:0] dadr sdam, sasz [7:0] sadr dsad 2-step register ddad 2-step register dmac 5-channel block diagram
mb91360g series 92 6. uart the uart is a serial i/o port for performing asynchronous (stop-start synchronization) communications. the mb91360g series contains three uart channels. (1) features ? full-duplex, double buffering ? supports asynchronous (stop-start synchronization) communications ? supports multi-processor mode ? fully programmable baud rate the baud rate can be set using an internal timer. (see the u-timer section.) ? supports flexible baud rate setting using an external clock ? error detection function (parity, framing, overrun) ? non return to zero (nrz) transfer signal ? supports dma transfer activation using an interrupt
mb91360g series 93 (2) register configuration register structure serial input register (sidr) serial output register (sodr) serial status register (ssr) serial mode register (smr) serial control register (scr) uart level select register (uls) address bits initial value smr 0000 0063 h 0000 006f h 0000 007b h 00 - - 0 - 00 b ? access address bits initial value scr 0000 0062 h 0000 006e h 0000 007a h 00000100 b ? access sidr (r)/sodr (w) smr scr r/w r/w access ssr uls 15 0 87 8 bits 8 bits 76543210 d6 d7 d5 d4 d3 d2 d1 d0 76543210 d6 d7 d5 d4 d3 d2 d1 d0 76543210 ore pe fre rdrf tdre ? rie tie 76543210 md0 md1 ?? cs0 ? scke ? 76543210 p pen sbl cl a/d rec rxe txe 76543210 ? ??? nsdo nsdi utdbl udbl r/w w 76543210 md2 r/w md1 reserved reserved cs0 reserved reserved reserved r/w r/w r/w r/w w r/w r/w 76543210 p r/w pen sbl cl a/d rec rxe txe
mb91360g series 94 ( 3 ) block diagram si md1 md0 cs0 scke soe pen p sbl cl a/d rec rxe txe pe ore fre rdrf tdre rie tie r - bus sidr sodr control signals control signals from u-timer (reception data) start bit detecter received bit counter received parity bit counter clock selection circuit reception status detecton circuit reception error occurrence signal for dma (to dmac) smr register scr register ssr register receiving clock reception control circuit reception shifter transmission shifter so (transmission data) reception completed start of transmission reception interrupt (to cpu) sck (clock) transmission interrupt (to cpu) transmitting clock transmission control circuit transmission start circuit transmission bit counter transmission parity counter
mb91360g series 95 7. u-timer (16-bit timer for uart baud rate generation) the u-timer (u-timer) is a 16-bit timer used to generate the baud rate for the uart. the operating frequency of the chip and the u-timer reload value can be combined to set a user-defined baud rate. the mb91360g series contains three u-timer channels. the intervaltimers can count for a maximum of 216 f . ( 1 ) block diagram utimr (reload register) utim (u-timer) clock load underflow to uart control f.f. 15 15 f (peripheral clock) 0 0
mb91360g series 96 (2) register configuration register structure utimr reload register utimc u timer control register utim address bits initial value access 0-ch 1-ch 2-ch 00000068 h 00000074 h 00000080 h 0r utimr address bits initial value access 0-ch 1-ch 2-ch 00000068 h 00000074 h 00000080 h 0w utimc address initial value access 0-ch 1-ch 2-ch 0000006b h 00000077 h 00000083 h 0---0001 r/w utimr utim w r/w r access r : read, w : write utimc drcl 15 0 87 15 14 2 1 0 b14 b15 b2 b1 b0 15 14 2 1 0 b14 b15 b2 b1 b0 76543210 ? ucc1 ?? undr reserved utst utcr
mb91360g series 97 8. pwm timer the pwm (pulse width modulation) timer can output high-precision pulse waves at an arbitrary cycle and pulse width (duty ratio) . the mb91360g series contains eight pwm timer channels. each of the channels consists of a 16-bit down- counter, cycle setting register, duty setting register, and pin controller. the control status register for each channel is used to indicate the operation status of the pwm timer. general control registers 1 and 2 are common registers shared by four channels, serving for input and software triggering. (1) features ? the count clock for the 16-bit down-counter can be selected from among the following four types : internal clocks : f , f /4, f /16, f /64 ( f : machine clock for peripherals) ? the counter can be initialized to ffff h by a reset or underflow. the 16-bit down-counter causes an underflow when it changes from 0000 h to ffff h . ? each channel has pwm outputs. eight channels : eight output pins ?registers cycle setting register : data reload register with buffer data transfer from the buffer is performed either when an activation trigger is detected or when the down-counter causes an underflow (cycle match) . the output is inverted at a cycle match. duty setting register : compare register with buffer. the value set in this register is compared to the counter value. the output is inverted when the values match (duty match) . ?pin control a duty match causes a reset to 1 (given priority) . an underflow causes a reset to 0. the output value fix mode enables output of all l or all h. the polarity can also be specified. ? interrupt requests can be generated by selecting the following interrupt sources : activation of the pwm timer (software trigger or trigger input) occurrence of an underflow (cycle match) occurrence of a duty match occurrence of an underflow (cycle match) or duty match ? you can set simultaneous activation of two or more channels using software or another interval timer. you can also set restarting the pwm timer during operation.
mb91360g series 98 (2) register configuration for channels 0 to 3 gcn10 bits gcn20 pdbl0 ptmr pcsr pdut pcnh pcnl ptmr pcsr pdut pcnh pcnl ptmr pcsr pdut pcnh r/w r/w r w w r/w r w w r/w r w w r/w 15 pwm timer ch 0 pwm timer ch 1 pwm timer ch 2 pwm timer ch 3 7 address access register name 0 8 0000011a h 00000126 h 0000012e h 00000136 h pcnl ptmr pcsr pdut pcnh pcnl r w w r/w general control register 10 disable/general control register 20 ch0 timer register ch0 cycle setting register ch0 duty setting register ch0 control status registers ch1 timer register ch1 cycle setting register ch1 duty setting register ch1 control status registers ch2 timer register ch2 cycle setting register ch2 duty setting register ch2 control status registers ch3 timer register ch3 cycle setting register ch3 duty setting register ch3 control status registers 0000013e h 00000118 h 00000124 h 0000012c h 00000134 h 0000013c h 00000122 h 0000012a h 00000132 h 0000013a h 00000120 h 00000128 h 00000130 h 00000138 h
mb91360g series 99 (3) pwm timer registers for channels 4 to 7 gcn11 bits gcn21 pdbl1 ptmr pcsr pdut pcnh pcnl ptmr pcsr pdut pcnh pcnl ptmr pcsr pdut pcnh r/w r/w r w w r/w r w w r/w r w w r/w 15 pwm timer ch 4 pwm timer ch 5 pwm timer ch 6 pwm timer ch 7 7 address access register name 0 8 0000011e h 00000146 h 0000014e h 00000156 h pcnl ptmr pcsr pdut pcnh pcnl r w w r/w general control register 11 disable/general control register 21 ch4 timer register ch4 cycle setting register ch4 duty setting register ch4 control status registers ch5 timer register ch5 cycle setting register ch5 duty setting register ch5 control status registers ch6 timer register ch6 cycle setting register ch6 duty setting register ch6 control status registers ch7 timer register ch7 cycle setting register ch7 duty setting register ch7 control status registers 0000015e h 0000011c h 00000144 h 0000014c h 00000154 h 0000015c h 00000142 h 0000014a h 00000152 h 0000015a h 00000140 h 00000148 h 00000150 h 00000158 h
mb91360g series 100 (4) configuration diagram of the entire pwm timer (5) configuration diagram of pwm timer 1 ch ocpa0 (pwm0) ch0 16-bit reload timer general control register 10 (source selection) output pins ch1 general control register 20 disable register 0 trg input pwm timer ch0 trg input pwm timer ch1 trg input pwm timer ch2 trg input pwm timer ch3 ocpa1 (pwm1) ocpa2 (pwm2) ocpa3 (pwm3) ocpa4 (pwm4) ch2 16-bit reload timer general control register 11 (source selection) ch3 general control register 21 disable register 1 trg input pwm timer ch4 trg input pwm timer ch5 trg input pwm timer ch6 trg input pwm timer ch7 ocpa5 (pwm5) ocpa6 (pwm6) ocpa7 (pwm7) f / 1 f / 4 f / 16 f / 64 clock trg input (internal trigger input) pwm output pcsr ppg mask enable software trigger inverted bit load pdut cmp interrupt selection edge detection start underflow prescalar 16-bit down-counter cycle setting register duty setting register peripheral clock ( f ) s r q irq (interrupt request signal)
mb91360g series 101 9. 16 - bit reload timer each 16-bit reload timer consists of a 16-bit down-counter, a 16-bit reload register, a prescaler for generating the internal count clock, and a control register. the 16-bit reload timer can also activate dma transfer using interrupts. the mb91360g series contains six 16-bit reload timer channels. (1) 16 bit reloard timer register configuration control status register (tmcsr) 16-bit timer register (tmr) 16-bit reload register (tmrlr) 15 14 13 12 11 10 9 8 ? ??? csl1 csl0 ?? 76543210 ? ?? reld inte uf cnte trg 15 0 15 0
mb91360g series 102 (2) block diagram reld ? ? inte uf cnte trg out ctl. csl1 csl0 16 8 16 2 f 2 1 f 2 3 f 2 5 gate uf irq 16-bit reload register reload 16-bit down-counter clock selector r-bus clear prescalar pwm (reload timer 0-ch to 3-ch)* a/d (reaload timer 4-ch)* * internally connected internal clock
mb91360g series 103 10. bit search module the bit search module searches for a 0, 1, or change-point in the data written to the input register and returns the position of the detected bit. this section describes the data register for detecting zeros (bsd0) , data register for detecting ones (bsd1) , data register for detecting change-points (bsdc) , and detection result register (bsrr) . a : data register for detecting zeros ( bsd0 ) b : date register for detecting ones ( bsd1 ) c : data register for detecting change points ( bsdc ) d : detection result register ( bsrr ) address initial value access 0000 03f0 h indeterminate w address initial value access 0000 03f4 h indeterminate r/w address initial value access 0000 03f8 h indeterminate w address initial value access 0000 03fc h indeterminate r 31 0 register structure 31 0 register structure 31 0 register structure 31 0 register structure
mb91360g series 104 block diagram of the bit search module d-bus input latch address decoder detection mode one-detect data conversion bit search circuit search result
mb91360g series 105 11. 10 - bi t a/d converter ( successive approximation conversion type ) this section provides an overview of the a/d converter, describes the register structure and functions, and describes the operation of the a/d converter. a/d converter converts analog input voltage into digital values, and provides the following features. ? conversion time : minimum 178 cycles (32 mhz : 5.6 m s, 24 mhz : 7.4 m s, 16 mhz : 11.2 m s) per channel ? rc type successive approximation conversion with sample & hold circuit ? 10-bit resolution ? program selection analog input from 16 channels single conversion mode : conversion of one selected channel scan conversion mode : continuous conversion of multiple channels, programmable for up to 16 channels single conversion mode : convert the specified channel once only. ? continuous mode : repeatedly convert the specified channels. ? stop mode : convert one channel then temporarily halt until the next activation. (enables synchronization of the conversion start timing.) ? a/d conversion can be followed by an a/d conversion interrupt request to cpu. this interrupt, an option that is ideal for continuous processing can be used to start a dma transfer of the results of a/d conversion to memory. ? startup may be by software, external trigger (falling edge) or timer (rising edge)
mb91360g series 106 channel setting register (adch) mode register (admd) control status register (adcs) data register (adcd) disable register (adbl) bit address : 00009d h bit address : 00009c h bit address : 00009f h bit address : 0000a1 h bit address : 0000a0 h bit address : 0000a3 h adcs adch admd adbl adcd 15 0 87 8 bit 8 bit 76543210 ans2 ans3 ans1 ans0 ane3 ane2 ane1 ane0 15 14 13 12 11 10 9 8 ? ??? mod1 mod0 sts1 sts0 76543210 int busy inte paus ?? strt reserved 76543210 d6 d7 d5 d4 d3 d2 d1 d0 15 14 13 12 11 10 9 8 ? ????? d9 d8 15 14 13 12 11 10 9 8 ? ? ? ???? dbl
mb91360g series 107 block diagram mpx d/a converter sequential comparison register sample-and-hold circuit comparator input circuit atgx decoder an0 an1 an2 an3 an4 an5 an6 an7 an8 an9 ana anb anc and ane anf adcd data bus a/d data register a/d channel setting register a/d mode register a/d control status register prescaler adch admd adcs operating clock av cc av rh /av rl av ss trigger activation machine clock ( f ) timer activation output of 16-bit reload timer 4 (internal connection)
mb91360g series 108 12. interrupt controller an interrupt controller controls interrupt acceptance and arbitration processing. hardware configuration this module consists of the following : icr register interrupt priority evaluation circuit interrupt level and interrupt number (vector) generator hold request cancel request generator major functions this module has the following major functions : detecting an nmi request or interrupt request priority evaluation (using the level or number) transferring the level of the interrupt cause in the evaluation result (to the cpu) transferring the number of the interrupt cause in the evaluation result (to the cpu) instructing recovery from stop mode due to an nmi or interrupt level other than 11111 (to the cpu) generating a hold request cancel request for the bus master
mb91360g series 109 (1) register configuration (continued) address : address : address : address : address : address : address : address : address : address : address : address : address : address : address : address : address : address : address : address : address : address : address : address : address : address : address : address : address : address : address : address : bit 7 6 5 4 3 2 1 0 ? ?? icr4 icr3 icr2 icr1 icr0 ? ?? icr4 icr3 icr2 icr1 icr0 ? ?? icr4 icr3 icr2 icr1 icr0 ? ?? icr4 icr3 icr2 icr1 icr0 ? ?? icr4 icr3 icr2 icr1 icr0 ? ?? icr4 icr3 icr2 icr1 icr0 ? ?? icr4 icr3 icr2 icr1 icr0 ? ?? icr4 icr3 icr2 icr1 icr0 ? ?? icr4 icr3 icr2 icr1 icr0 ? ?? icr4 icr3 icr2 icr1 icr0 ? ?? icr4 icr3 icr2 icr1 icr0 ? ?? icr4 icr3 icr2 icr1 icr0 ? ?? icr4 icr3 icr2 icr1 icr0 ? ?? icr4 icr3 icr2 icr1 icr0 ? ?? icr4 icr3 icr2 icr1 icr0 ? ?? icr4 icr3 icr2 icr1 icr0 ? ?? icr4 icr3 icr2 icr1 icr0 ? ?? icr4 icr3 icr2 icr1 icr0 ? ?? icr4 icr3 icr2 icr1 icr0 ? ?? icr4 icr3 icr2 icr1 icr0 ? ?? icr4 icr3 icr2 icr1 icr0 ? ?? icr4 icr3 icr2 icr1 icr0 ? ?? icr4 icr3 icr2 icr1 icr0 ? ?? icr4 icr3 icr2 icr1 icr0 ? ?? icr4 icr3 icr2 icr1 icr0 ? ?? icr4 icr3 icr2 icr1 icr0 ? ?? icr4 icr3 icr2 icr1 icr0 ? ?? icr4 icr3 icr2 icr1 icr0 ? ?? icr4 icr3 icr2 icr1 icr0 ? ?? icr4 icr3 icr2 icr1 icr0 ? ?? icr4 icr3 icr2 icr1 icr0 ? ?? icr4 icr3 icr2 icr1 icr0 icr00 icr01 icr02 icr03 icr04 icr05 icr06 icr07 icr08 icr09 icr10 icr11 icr12 icr13 icr14 icr15 icr16 icr17 icr18 icr19 icr20 icr21 icr22 icr23 icr24 icr25 icr26 icr27 icr28 icr29 icr30 icr31 00000440 h 00000441 h 00000442 h 00000443 h 00000444 h 00000445 h 00000446 h 00000447 h 00000448 h 00000449 h 0000044a h 0000044b h 0000044c h 0000044d h 0000044e h 0000044f h 00000450 h 00000451 h 00000452 h 00000453 h 00000454 h 00000455 h 00000456 h 00000457 h 00000458 h 00000459 h 0000045a h 0000045b h 0000045c h 0000045d h 0000045e h 0000045f h r r/w r/w r/w r/w
mb91360g series 110 (continued) address : address : address : address : address : address : address : address : address : address : address : address : address : address : address : address : address : bit 7 6 5 4 3 2 1 0 ? ?? icr4 icr3 icr2 icr1 icr0 ? ?? icr4 icr3 icr2 icr1 icr0 ? ?? icr4 icr3 icr2 icr1 icr0 ? ?? icr4 icr3 icr2 icr1 icr0 ? ?? icr4 icr3 icr2 icr1 icr0 ? ?? icr4 icr3 icr2 icr1 icr0 ? ?? icr4 icr3 icr2 icr1 icr0 ? ?? icr4 icr3 icr2 icr1 icr0 ? ?? icr4 icr3 icr2 icr1 icr0 ? ?? icr4 icr3 icr2 icr1 icr0 ? ?? icr4 icr3 icr2 icr1 icr0 ? ?? icr4 icr3 icr2 icr1 icr0 ? ?? icr4 icr3 icr2 icr1 icr0 ? ?? icr4 icr3 icr2 icr1 icr0 ? ?? icr4 icr3 icr2 icr1 icr0 ? ?? icr4 icr3 icr2 icr1 icr0 r r/w r/w r/w r/w ? mhalti ? lvl4 lvl3 lvl2 lvl1 lvl0 r r/w r/w r/w r/w r/w icr32 icr33 icr34 icr35 icr36 icr37 icr38 icr39 icr40 icr41 icr42 icr43 icr44 icr45 icr46 icr47 hrcl 00000460 h 00000461 h 00000462 h 00000463 h 00000464 h 00000465 h 00000466 h 00000467 h 00000468 h 00000469 h 0000046a h 0000046b h 0000046c h 0000046d h 0000046e h 0000046f h 00000045 h
mb91360g series 111 (2) block diagram r100 r147 (dlyirq) 5 6 level4 to 0 mhalt1 vct5 to 0 r-bus unmi wakeup (1 if level = 11111) priority evaluation level evaluation nmi processing icr00 vector evaluation level and vector generation hldreq withdrawal request icr47 nmirq (nmi request)
mb91360g series 112 13. external interrupt/nmi control block the external interrupt/nmi controller controls external interrupt requests input from the nmi and int0 to int7 pins. detection of h levels, l levels, rising edges, or falling edges can be selected (except for the nmi) . the external interrupt/nmi controller can also be used for dma requests. this section lists the registers of the controller and provides its block diagram. (1) register configuration of the external interrupt nmi controller (2) block diagram external interruption permission register (enir) external interruption factors register (eirr) request level setting register (elvr) bit bit bit bit 7654 321 0 en6 en7 en5 en4 en3 en2 en1 en0 15 14 13 12 11 10 9 8 er6 er7 er5 er4 er3 er2 er1 er0 15 14 13 12 11 10 9 8 la7 lb7 lb6 la6 lb5 la5 lb4 la4 7654 321 0 la3 lb3 lb2 la2 lb1 la1 lb0 la0 9 9 int0 to 7 nmix 8 8 8 r bus interrupt request enable interrupt request register gate request f/f edge detect circuit external interrupt request register external level register
mb91360g series 113 14. delayed interrupt delayed interrupt control register (dicr) the delayed interrupt control register (dicr) is a delayed interrupt generator register and is used to generate the task switching interrupt. structure of the dicr address bits initial value 00000044 h - - - - - - - 0 ? access r/w 76543210 ? ? ? ???? dlyi
mb91360g series 114 15. clock generation the mb91v360 generates internal operating clocks as follows : base clock generation : device scales clock source input by 2 (x clock) or oscillates base clock with pll to generate basic clock (pll clock) generation of each internal clock : device scales base clock to generate clocks supplied to each block generation and control of each clock are explained below. some devices allow the operation of the rtc module based on a separate 32 khz subclock. see the section about subclock operation for more details. (1) register configuration (continued) rsrr : reset source register , watchdog timer control register * : varies with reset factor x : not initialized ** : after execution of the program in the internal boot rom the reset source is visible stcr : standby control register * : valid only when this initialization is performed simultaneously with initialization by initx : others same as init. bit address : 00000480 h access initial value (initx) initial value (init) initial value (rst) after boot rom ** bit address : 00000481 h access initial value (initx) initial value (hstx) * initial value (init) initial value (rst) r 0 * x 0 r 0 * x 0 r 0 x * 0 r 0 x * 0 ? ? ? ? 0 r/w 0 0 0 0 r/w 0 0 0 0 15 14 13 12 11 10 9 8 hstb r 1 * x 0 init wdog erst srst ? wt1 wt0 r/w 0 0 0 0 r/w 1 1 1 x r/w 1 1 1 1 r/w 0 1 x x r/w 0 1 x x r/w 1 1 1 x r/w 1 1 1 x 76543210 sleep r/w 0 0 0 0 stop hiz srst os1 os0 oscd2 oscd1
mb91360g series 115 (continued) tbcr : time - based counter control registe r ctbr : time - based counter clear register clkr : clock source control register wpr watchdog reset generation postponement register divr0 : base clock division setting register 0 divr1 : base clock division setting register 1 bit address : 00000482 h initial value (init) initial value (rst) bit address : 00000483 h initial value (init) initial value (rst) bit address : 00000484 h initial value (init) initial value (rst) bit address : 00000485 h initial value (init) initial value (rst) bit address : 00000486 h initial value (init) initial value (rst) bit address : 00000487 h initial value (init) initial value (rst) 0 0 r/w x x r/w x x r/w x x r/w x x r/w 0 x r/w 0 x r/w 15 14 13 12 11 10 9 8 tbie 0 0 r/w tbif tbc2 tbc1 tbc0 ? syncr syncs x x w x x w x x w x x w x x w x x w x x w 76543210 d6 x x w d7 d5 d4 d3 d2 d1 d0 r/w 0 x r/w 0 x r/w 0 x r/w 0 x r/w 0 x r/w 0 x r/w 0 x 15 14 13 12 11 10 9 8 pll1s2 r/w 0 x pll2s0 pll1s1 pll1s0 pll2en pll1en clks1 clks0 r/w x x r/w x x r/w x x r/w x x r/w x x r/w x x r/w x x 76543210 d6 r/w x x d7 d5 d4 d3 d2 d1 d0 r/w 0 x r/w 0 x r/w 0 x r/w 0 x r/w 0 x r/w 1 x r/w 1 x 76543210 b2 r/w 0 x b3 b1 b0 p3 p2 p1 p0 r/w 0 x r/w 0 x r/w 0 x r/w 0 x r/w 0 x r/w 0 x r/w 0 x 76543210 t2 r/w 0 x t3 t1 t0 s3 s2 s1 s0
mb91360g series 116 (continued) cmcr : clock control for can modules subclock rtc32 ( clkr2 ) this register is used to control the rtc32 mode bit for use in subclock system. address initial 0164 h 11111111 address initial 0165 h 00000000 address 000046 h access initial value bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 pre6 pre7 pre5 pre4 pre3 pre2 pre1 pre0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ? pres ?????? r/w 0 r/w 0 r/w 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 ? ? ? ???? rtc32
mb91360g series 117 (2) block diagram r b u s selclk x0 x1 x0a x1a oscillator circuit 4 mhz oscillator circuit 32 khz internal interrrupt internal reset hstx rstx initx divr0 and divr1 registers [clock generation block] stop control cpu clock clkb ext. bus clock clkt resource clock clkp monclk clock for rtc clock for can canclk internal reset (rst) sleep state stop state internal reset (init) cpu clock division resource clock division ext. bus clock division clkr register pll1 1/2 clock mod 1 0 [stop/sleep control block] reset occurrence f/f reset occurrence f/f stcr register state transition control circuit rsrr register [reset source circuit] wpr register ctbr register tbcr register watchdog f/f timer-base counter overflow detect. f/f [watchdog control block] time-base timer interrupt request interrupt enable
mb91360g series 118 16. bus interface the external bus interface controls the interfaces with the external memory and external i/os. ? up to 32-bit (4 gb) address output. ? up to eight independent banks provided by chip-select function the banks can be set in 64-kb (minimum) at any position in the logic address space. can be set to no area ? 32/16/8 bit bus width setup can be performed for each chip-select area. ? programmable automatic memory wait (up to 7 cycles) insertion ? unused address/data pins can be used as i/o ports. (but see notes below) note : chip select area cs7 is used for the internal can modules. the necessary register settings are done by an internal boot routine. take care not to overwrite register bits related to this cs area. if the can macros which are connected internally to the external bus (also called user logic bus) are used, a certain number of data, address and control ports of the external bus interface cannot be configured as general purpose io ports. (1) register configuration (continued) area select registers ( asr0 to asr7 ) after execution of the code in the initial boot rom asr0 is set to 0x20, and asr7 to 0x10. asr0 initial value access init rst 00000640 h 0000 h 0000 h w asr1 initial value access init rst 00000644 h 0000 h xxxx h w asr2 initial value access init rst 00000648 h 0000 h xxxx h w asr3 initial value access init rst 0000064c h 0000 h xxxx h w asr4 initial value access init rst 0000650 h 0000 h xxxx h w asr5 initial value access init rst 00000654 h 0000 h xxxx h w asr6 initial value access init rst 00000658 h 0000 h xxxx h w asr7 initial value access init rst 0000065c h 0000 h xxxx h w 15 14 13 12 2 1 0 a30 a31 a29 po4 po3 a18 a17 a16 . . . . . . . . . 15 14 13 12 2 1 0 a30 a31 a29 po4 po3 a18 a17 a16 . . . . . . . . . 15 14 13 12 2 1 0 a30 a31 a29 po4 po3 a18 a17 a16 . . . . . . . . . 15 14 13 12 2 1 0 a30 a31 a29 po4 po3 a18 a17 a16 . . . . . . . . . 15 14 13 12 2 1 0 a30 a31 a29 po4 po3 a18 a17 a16 . . . . . . . . . 15 14 13 12 2 1 0 a30 a31 a29 po4 po3 a18 a17 a16 . . . . . . . . . 15 14 13 12 2 1 0 a30 a31 a29 po4 po3 a18 a17 a16 . . . . . . . . . 15 14 13 12 2 1 0 a30 a31 a29 po4 po3 a18 a17 a16 . . . . . . . . .
mb91360g series 119 (continued) area mask register ( amr0 to amr7 ) area mode registers ( amd0 to amd7 ) che ( cache enable register ) cse ( chip select enable register ) amr0 initial value access init rst 00000642 h ffff h ffff h w amr1 initial value access init rst 00000646 h 0000 h xxxx h w amr2 initial value access init rst 0000064a h 0000 h xxxx h w amr3 initial value access init rst 0000064e h 0000 h xxxx h w amr4 initial value access init rst 0000652 h 0000 h xxxx h w amr5 initial value access init rst 00000656 h 0000 h xxxx h w amr6 initial value access init rst 0000065a h 0000 h xxxx h w amr7 initial value access init rst 0000065e h 0000 h xxxx h w 00000660 h 00000111 b r / w 00000670 h 11111111 b r / w 00000668 h 00000001 b r / w 15 14 13 12 2 1 0 a30 a31 a29 po4 po3 a18 a17 a16 . . . . . . . . . 15 14 13 12 2 1 0 a30 a31 a29 po4 po3 a18 a17 a16 . . . . . . . . . 15 14 13 12 2 1 0 a30 a31 a29 po4 po3 a18 a17 a16 . . . . . . . . . 15 14 13 12 2 1 0 a30 a31 a29 po4 po3 a18 a17 a16 . . . . . . . . . 15 14 13 12 2 1 0 a30 a31 a29 po4 po3 a18 a17 a16 . . . . . . . . . 15 14 13 12 2 1 0 a30 a31 a29 po4 po3 a18 a17 a16 . . . . . . . . . 15 14 13 12 2 1 0 a30 a31 a29 po4 po3 a18 a17 a16 . . . . . . . . . 15 14 13 12 2 1 0 a30 a31 a29 po4 po3 a18 a17 a16 . . . . . . . . . ? ? rdye bw1 bw0 wtc2 wtc1 wtc0 che6 che7 che5 che4 che3 che2 che1 che0 cse6 cse7 cse5 cse4 cse3 cse2 cse1 cse0
mb91360g series 120 (2) block diagram mux address bus data bus cs0x to cs7x rdx wr0x, wr1x wr2x, wr3x brq bgrntx rdy clk 32 32 write bus read buffer switch a-out switch + 1 or + 2 address buffer asr asz comparator all block control data block external data bus external address bus address block resisters & control external pin control section
mb91360g series 121 17. can controller this section provides an overview of the can interface, describes the register structure and functions, and describes the operation of the can interface. the can controller is a module built into a mb91360g series. the can (controller area network) is the standard protocol for serial communication between automobile controllers and is widely used in industrial applications. the can controller has the following features : ? conforms to can specification version 2.0 part a and b - supports transmission/reception in standard frame and extended frame formats ? supports transmitting of data frames by receiving remote frames ? 16 transmitting/receiving message buffers - 29-bit id and 8-byte data - multi-level message buffer configuration ? supports full-bit comparison, full-bit mask and partial bit mask filtering. - two acceptance mask registers in either standard frame format or extended frame formats ? bit rate programmable from 10 kbits/s to 1 mbits/s (when input clock is at 16 mhz) the following sections only describe can 0. for the addresses of the registers of the other can channels see the io-map. the address shown assume that the cs7 area is defined as described in the chapter about the internal boot rom.
mb91360g series 122 (1) list of control registers list of control registers ( 1 ) address register abbreviation access initial value can0 100000 h message buffer valid register bvalr0 r/w 00000000 00000000 100001 h 100002 h transmit request register treqr0 r/w 00000000 00000000 100003 h 100004 h transmit cancel register tcanr0 w 00000000 00000000 100005 h 100006 h transmit complete register tcr0 r/w 00000000 00000000 100007 h 100008 h receive complete register rcr0 r/w 00000000 00000000 100009 h 10000a h remote request receiving register rrtrr0 r/w 00000000 00000000 10000b h 10000c h receive overrun register rovrr0 r/w 00000000 00000000 10000d h 10000e h receive interrupt enable register rier0 r/w 00000000 00000000 10000f h 100010 h control status register csr0 r/w, r 00 - - - 000 0 - - - - 0 - 1 100011 h 100012 h last event indicator register leir0 r/w - - - - - - - - 000 - 0000 100013 h 100014 h receive/transmit error counter rtec0 r 00000000 00000000 100015 h 100016 h bit timing register btr0 r/w -1111111 11111111 100017 h 100018 h ide register ider0 r/w xxxxxxxx xxxxxxxx 100019 h
mb91360g series 123 list of control registers ( 2 ) address register abbreviation access initial value can0 10001a h transmit rtr register trtrr0 r/w 00000000 00000000 10001b h 10001c h remote frame receive waiting register rfwtr0 r/w xxxxxxxx xxxxxxxx 10001d h 10001e h transmit interrupt enable register tier0 r/w 00000000 00000000 10001f h 100020 h acceptance mask select register amsr0 r/w xxxxxxxx xxxxxxxx 100021 h 100022 h xxxxxxxx xxxxxxxx 100023 h 100024 h acceptance mask register 0 amr00 r/w xxxxxxxx xxxxxxxx 100025 h 100026 h xxxxx - - - xxxxxxxx 100027 h 100028 h acceptance mask register 1 amr10 r/w xxxxxxxx xxxxxxxx 100029 h 10002a h xxxxx - - - xxxxxxxx 10002b h
mb91360g series 124 (2) message buffers list of message buffers (id registers) (1) address register abbreviation access initial value can0 10002c h to 10004b h general-purpose ram ? r/w xxxxxxxx to xxxxxxxx 10004c h id register 0 idr00 r/w xxxxxxxx xxxxxxxx 10004d h 10004e h xxxxx - - - xxxxxxxx 10004f h 100050 h id register 1 idr10 r/w xxxxxxxx xxxxxxxx 100051 h 100052 h xxxxx - - - xxxxxxxx 100053 h 100054 h id register 2 idr20 r/w xxxxxxxx xxxxxxxx 100055 h 100056 h xxxxx - - - xxxxxxxx 100057 h 100058 h id register 3 idr30 r/w xxxxxxxx xxxxxxxx 100059 h 10005a h xxxxx - - - xxxxxxxx 10005b h 10005c h id register 4 idr40 r/w xxxxxxxx xxxxxxxx 10005d h 10005e h xxxxx - - - xxxxxxxx 10005f h 100060 h id register 5 idr50 r/w xxxxxxxx xxxxxxxx 100061 h 100062 h xxxxx - - - xxxxxxxx 100063 h 100064 h id register 6 idr60 r/w xxxxxxxx xxxxxxxx 100065 h 100066 h xxxxx - - - xxxxxxxx 100067 h
mb91360g series 125 list of message buffers ( id registers ) ( 2 ) address register abbreviation access initial value can0 100068 h id register 7 idr70 r/w xxxxxxxx xxxxxxxx 100069 h 10006a h xxxxx - - - xxxxxxxx 10006b h 10006c h id register 8 idr80 r/w xxxxxxxx xxxxxxxx 10006d h 10006e h xxxxx - - - xxxxxxxx 10006f h 100070 h id register 9 idr90 r/w xxxxxxxx xxxxxxxx 100071 h 100072 h xxxxx - - - xxxxxxxx 100073 h 100074 h id register 10 idr10 r/w xxxxxxxx xxxxxxxx 100075 h 100076 h xxxxx - - - xxxxxxxx 100077 h 100078 h id register 11 idr11 r/w xxxxxxxx xxxxxxxx 100079 h 10007a h xxxxx - - - xxxxxxxx 10007b h 10007c h id register 12 idr12 r/w xxxxxxxx xxxxxxxx 10007d h 10007e h xxxxx - - - xxxxxxxx 10007f h 100080 h id register 13 idr13 r/w xxxxxxxx xxxxxxxx 100081 h 100082 h xxxxx - - - xxxxxxxx 100083 h 100084 h id register 14 idr14 r/w xxxxxxxx xxxxxxxx 100085 h 100086 h xxxxx - - - xxxxxxxx 100087 h
mb91360g series 126 list of message buffers (id registers) (3) list of message buffers (dlc registers and data registers) (1) address register abbreviation access initial value can0 100088 h id register 15 idr15 r/w xxxxxxxx xxxxxxxx 100089 h 10008a h xxxxx - - - xxxxxxxx 10008b h address register abbreviation access initial value can0 10008c h dlc register 0 dlcr00 r/w - - - - xxxx 10008d h 10008e h dlc register 1 dlcr10 r/w - - - - xxxx 10008f h 100090 h dlc register 2 dlcr20 r/w - - - - xxxx 100091 h 100092 h dlc register 3 dlcr30 r/w - - - - xxxx 100093 h 100094 h dlc register 4 dlcr40 r/w - - - - xxxx 100095 h 100096 h dlc register 5 dlcr50 r/w - - - - xxxx 100097 h 100098 h dlc register 6 dlcr60 r/w - - - - xxxx 100099 h 10009a h dlc register 7 dlcr70 r/w - - - - xxxx 10009b h 10009c h dlc register 8 dlcr80 r/w - - - - xxxx 10009d h 10009e h dlc register 9 dlcr90 r/w - - - - xxxx 10009f h 1000a0 h dlc register 10 dlcr100 r/w - - - - xxxx 1000a1 h
mb91360g series 127 list of message buffers (dlc registers and data registers) (2) address register abbreviation access initial value can0 1000a2 h dlc register 11 dlcr110 r/w - - - - xxxx 1000a3 h 1000a4 h dlc register 12 dlcr120 r/w - - - - xxxx 1000a5 h 1000a6 h dlc register 13 dlcr130 r/w - - - - xxxx 1000a7 h 1000a8 h dlc register 14 dlcr140 r/w - - - - xxxx 1000a9 h 1000aa h dlc register 15 dlcr150 r/w - - - - xxxx 1000ab h 1000ac h to 1000b3 h data register 0 (8 bytes) dtr00 r/w xxxxxxxx to xxxxxxxx 1000b4 h to 1000bb h data register 1 (8 bytes) dtr10 r/w xxxxxxxx to xxxxxxxx 1000bc h to 1000c3 h data register 2 (8 bytes) dtr20 r/w xxxxxxxx to xxxxxxxx 1000c4 h to 1000cb h data register 3 (8 bytes) dtr30 r/w xxxxxxxx to xxxxxxxx 1000cc h to 1000d3 h data register 4 (8 bytes) dtr40 r/w xxxxxxxx to xxxxxxxx 1000d4 h to 1000db h data register 5 (8 bytes) dtr50 r/w xxxxxxxx to xxxxxxxx 1000dc h to 1000e3 h data register 6 (8 bytes) dtr60 r/w xxxxxxxx to xxxxxxxx 1000e4 h to 1000eb h data register 7 (8 bytes) dtr70 r/w xxxxxxxx to xxxxxxxx 1000ec h to 1000f3 h data register 8 (8 bytes) dtr80 r/w xxxxxxxx to xxxxxxxx 1000f4 h to 1000fb h data register 9 (8 bytes) dtr90 r/w xxxxxxxx to xxxxxxxx
mb91360g series 128 list of message buffers (dlc registers and data registers) (3) configuration register ( creg ) address register abbreviation access initial value can0 1000fc h to 100103 h data register 10 (8 bytes) dtr100 r/w xxxxxxxx to xxxxxxxx 100104 h to 10010b h data register 11 (8 bytes) dtr110 r/w xxxxxxxx to xxxxxxxx 10010c h to 100113 h data register 12 (8 bytes) dtr120 r/w xxxxxxxx to xxxxxxxx 100114 h to 10011b h data register 13 (8 bytes) dtr130 r/w xxxxxxxx to xxxxxxxx 10011c h to 100123 h data register 14 (8 bytes) dtr140 r/w xxxxxxxx to xxxxxxxx 100124 h to 10012b h data register 15 (8 bytes) dtr150 r/w xxxxxxxx to xxxxxxxx address register abbreviation access initial value can0 10012c h 10012d h configuration register creg0 r/w 00000000 00000110
mb91360g series 129 (3) block diagram btr psc creg canclk clkt pr ph rsj toe ns1,0 nt nie halt rs ts csr rtec bvalr treqr tcanr trtrr rfwtr tcr tier rcr rier rrtrr rovrr amsr amr0 amr1 leir idr0 to 15, dlcr0 to 15, dtr0 to 15, ram 0 1 rbf x , tbf x , rdlc, tdlc, idsel rbf x idsel tbf x tbf x ph1 rx frmer acker biter arblost stfer rdlc crcer tdlc tdlc rdlc idsel arblost tx biter, stfer, crcer, frmer, acker sync, tseg1, tseg2 tq (operating clock) clock configuration clock for can transmit/receive operation clock for external bus access external bus (user logic bus) prescaler 1 to 64 frequency division bit timing generation node status change interrupt generation node status change interrupt bus state machine idle, int, suspnd, transmit, receive, err, ovrld error control transmitting/ receiving sequencer tbfx, clear transmitting buffer x decision data counter acceptance filter control error frame generation overload frame generation output driver transmission shift register stuffing tbfx, set, clear crc generation ack generation transmission complete interrupt generator transmission complete interrupt rbfx, set crc generator/ error check reception complete interrupt generation reception completed interrupt rbfx, tbfx, set, clear receive shift register destuffing/ stuffing error check rbfx, set arbitration check bit error check acceptance filter receiving buffer x decision acknowledgment error check form error check input latch ram address generation
mb91360g series 130 18. d/a converter this section provides an overview of the d/a converter, describes the register structure and functions, and describes the operarton of d/a converter.this block is an r-2r format d/a converter, having ten-bit resolution. the d/a converter has two channels.output control can be performed independently for the two channels using the d/a control register. (1) block diagram da 17 da 16 da 15 da 19 da 18 da 14 da 13 da 12 da 11 da 10 da 07 da 06 da 05 da 09 r-bus da 08 da 04 da output ch1 da output ch0 da 03 da 02 da 01 da 00 dae1 standby control 2r 2r 2r 2r r r r dvr da19 da18 da17 da11 da10 dae0 standby control 2r 2r 2r 2r r r r dvr da09 da08 da07 da01 da00 2r 2r
mb91360g series 131 (2) registers d / a control register (dacr) d / a converter data register (ch 0) (dadr0) d / a converter data register (ch 1) (dadr1) d/a clock control (ddbl) bit address : 0000a5 h bit address : 0000a6 h bit address : 0000a7 h bit address : 0000a8 h bit address : 0000a9 h bit address : 0000ab h 76543210 ? ???? mode dae1 dae0 15 14 13 12 11 10 9 8 ? ????? da09 da08 76543210 da06 da07 da05 da04 da03 da02 da01 da00 15 14 13 12 11 10 9 8 ? ????? da19 da18 76543210 da16 da17 da15 da14 da13 da12 da11 da10 76543210 ? ? ? ???? dbl
mb91360g series 132 19. 100 khz i 2 c interface this section describes the functions and operation of the mb91360g series basic i 2 c interface. this interface allows operation up to 100 khz and 8-bit-addressing. the i 2 c interface is a serial i/o port supporting the inter ic bus, operating as a master/slave device on the i 2 c bus. (1) i 2 c interface features the mb91360g series microcontroller includes a built-in one-channel i 2 c interface. the i 2 c interface has the following features. ? master/slave sending and receiving functions ? arbitration function ? clock synchronization function ? slave address/general call address detection function ? transfer direction detection function ? repeated start condition generation and detection function ? bus error detection function
mb91360g series 133 (2) i 2 c interface registers a : bus status register ( ibsr ) b : bus control register ( ibcr ) c : clock control register ( iccr ) d : address register ( iadr ) e : data register ( idar ) f : clock disable register ( idbl ) bit no. address : 000095 h read/write default value bit no. address : 000094 h read/write default value bit no. address : 000097 h read/write default value bit no. address : 000096 h read/write default value bit no. address : 000099 h read/write default value bit no. address : 00009b h read/write default value ( r ) ( 0 ) ( r ) ( 0 ) ( r ) ( 0 ) ( r ) ( 0 ) ( r ) ( 0 ) ( r ) ( 0 ) ( r ) ( 0 ) 76543210 rsc ( r ) ( 0 ) bb al lrb trx aas gca fbt (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) 15 14 13 12 11 10 9 8 beie (r/w) ( 0 ) ber scc mss ack gcaa inte int ( ? ) ( ? ) (r/w) ( 0 ) (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) 76543210 ? ( ? ) ( ? ) ? en cs4 cs3 cs2 cs1 cs0 (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) 15 14 13 12 11 10 9 8 a6 ( ? ) ( ? ) ? a5 a4 a3 a2 a1 a0 (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) 76543210 d6 (r/w) ( x ) d7 d5 d4 d3 d2 d1 d0 ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) (r/w) ( 0 ) 76543210 ? ( ? ) ( ? ) ? ? ???? dbl
mb91360g series 134 (3) i 2 c interface block diagram iccr en iccr ibsr bb rsc lrb trx fbt al ibcr ber beie inte int ibcr r-bus scc mss ack gcaa ibsr idar iadr aas gca cs4 cs3 cs2 cs1 cs0 2 4 8 16 128 256 32 64 56 78 sync shift clock generator start-stop condition deector arbitration lost detectior interrupt request end start-stop condition detector slave address comparator clock divider 1 clock selector 1 clock divider 2 clock selector 2 first byte error i 2 c enable clock signal for division shift clock edge conversion timing bus busy repeat start send/receive start master slave global call ack enable gc-ack enable last bit scl sda
mb91360g series 135 20. 400 khz i 2 c interface this section describes the functions and operation of the fast i 2 c interface. the i 2 c interface is a serial i/o port supporting the inter ic bus, operating as a master/slave device on the i 2 c bus. (1) features ? master/slave transmitting and receiving functions ? arbitration function ? clock synchronization function ? general call addressing support ? transfer direction detection function ? repeated start condition generation and detection function ? bus error detection function ? 7 bit addressing as master and slave ? 10 bit addressing as master and slave ? possibility to give the interface a seven and a ten bit slave address ? acknowledging upon slave address reception can be disabled (master-only operation) ? address masking to give interface several slave addresses (in 7 and 10 bit mode) ? up to 400 kbit transfer rate ? possibility to use built-in noise filters for sda and scl ? can receive data at 400 kbit if r-bus-clock is higher than 6 mhz regardless of prescaler setting ? can generate mcu interrupts on transmission and bus error events ? supports being slowed down by a slave on bit and byte level the i 2 c interface does not support scl clock stretching on bit level since it can receive the full 400 kbit datarate if the r-bus-clock (clkp) is higher than 6 mhz regardless of the prescaler setting. however, clock stretching on byte level is performed since scl is pulled low during an interrupt (int = 1 in ibcr register) .
mb91360g series 136 (2) block diagram idbl dbl clock disable clock divider 1 clock selector clock divider 2 (by 12) scl duty cycle generator iccr 55 ibsr bb rsc lrb trx adt al ibcr ber beie inte int ibcr r-bus scc mss ack gcaa ibsr idar aas gca ismk itmk entb ral itmk itba isba ismk ensb cs4 cs3 cs2 cs1 cs0 2345 32 sync interrupt request start-stop condition generator ack generator slave address comparator bus observer arbitration loss detector shift clock generator address data bus error mcu irq scl sda scl enable sda bus busy r-bus clock (clkp) fb59 module clock supply repeat start send/receive start master slave general call ack enable gc-ack enable enable 7 bit mode enable 10 bit mode received ad. length last bit nsf noise filter iccr 8 10 10 7 10 7 10 8
mb91360g series 137 (3) i 2 c interface registers (continued) a : bus control register ( ibcr2 ) b : bus status register ( ibsr2 ) c : ten bit slave address register ( itbah , itbal ) ten bit address high byte ten bit address low byte d : ten bit slave address mask register ( itmkh , itmkl ) ten bit address mask high byte ten bit address mask low byte e : seven bit slave address register ( isba ) bit no. address : 000184 h read/write default value bit no. address : 000185 h read/write default value bit no. address : 000186 h read/write default value bit no. address : 000187 h read/write default value bit no. address : 000188 h read/write default value bit no. address : 000189 h read/write default value bit no. address : 00018b h read/write default value (r/w) ( 0 ) ( w ) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) 15 14 13 12 11 10 9 8 beie (r/w) ( 0 ) ber scc mss ack gcaa inte int ( r ) ( 0 ) ( r ) ( 0 ) ( r ) ( 0 ) ( r ) ( 0 ) ( r ) ( 0 ) ( r ) ( 0 ) ( r ) ( 0 ) 76543210 rsc ( r ) ( 0 ) bb al lrb trx aas gca fbt ( ? ) ( 0 ) ( ? ) ( 0 ) ( ? ) ( 0 ) ( ? ) ( 0 ) ( ? ) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) 15 14 13 12 11 10 9 8 ? ( ? ) ( 0 ) ????? ta9 ta8 (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) 76543210 ta6 (r/w) ( 0 ) ta7 ta5 ta4 ta3 ta2 ta1 ta0 ( r ) ( 0 ) ( ? ) ( 1 ) ( ? ) ( 1 ) ( ? ) ( 1 ) ( ? ) ( 1 ) (r/w) ( 1 ) (r/w) ( 1 ) 15 14 13 12 11 10 9 8 ral (r/w) ( 0 ) entb ???? tm9 tm8 (r/w) ( 1 ) (r/w) ( 1 ) (r/w) ( 1 ) (r/w) ( 1 ) (r/w) ( 1 ) (r/w) ( 1 ) (r/w) ( 1 ) 76543210 tm6 (r/w) ( 1 ) tm7 tm5 tm4 tm3 tm2 tm1 tm0 (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) 76543210 sa6 ( ? ) ( 0 ) ? sa5 sa4 sa3 sa2 sa1 sa0
mb91360g series 138 (continued) f : seven bit slave address mask register ( ismk ) g : data register ( idarh , idar2 ) data register high byte data register h : clock control register ( iccr2 ) i : clock disable register ( idbl2 ) bit no. address : 00018a h read/write default value bit no. address : 00018c h read/write default value bit no. address : 00018d h read/write default value bit no. address : 00018e h read/write default value bit no. address : 00018f h read/write default value (r/w) ( 1 ) (r/w) ( 1 ) (r/w) ( 1 ) (r/w) ( 1 ) (r/w) ( 1 ) (r/w) ( 1 ) (r/w) ( 1 ) 15 14 13 12 11 10 9 8 sm6 (r/w) ( 0 ) ensb sm5 sm4 sm3 sm2 sm1 sm0 ( ? ) ( 0 ) ( ? ) ( 0 ) ( ? ) ( 0 ) ( ? ) ( 0 ) ( ? ) ( 0 ) ( ? ) ( 0 ) ( ? ) ( 0 ) 15 14 13 12 11 10 9 8 ? ( ? ) ( 0 ) ? ? ????? (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) 76543210 d6 (r/w) ( 0 ) d7 d5 d4 d3 d2 d1 d0 (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 1 ) (r/w) ( 1 ) (r/w) ( 1 ) (r/w) ( 1 ) (r/w) ( 1 ) 15 14 13 12 11 10 9 8 nsf ( ? ) ( 0 ) ? en cs4 cs3 cs2 cs1 cs0 ( ? ) ( 0 ) ( ? ) ( 0 ) ( ? ) ( 0 ) ( ? ) ( 0 ) ( ? ) ( 0 ) ( ? ) ( 0 ) (r/w) ( 0 ) 76543210 ? ( ? ) ( 0 ) ? ? ???? dbl
mb91360g series 139 21. 16-bit i/o timer the mb91360g series contains two 16-bit free-running timer modules, two output compare modules, and two input capture modules and supports four input channels and four output channels. the following sections only describes the 16-bit free-running timer, output compare 0/1 and input capture 0/1. the remaining modules have the identical functions and the register addresses should be found in the i/o map. (1) function overview a : 16 - bit free - running timer the 16-bit free-run timer consists of a 16-bit up counter, control register, and prescaler. the values output from this timer counter are used as the base timer for input capture and output compare. ? four counter clocks are available. internal clock : f /4, f /16, f /32, f /64 ? an interrupt can be generated upon a counter overflow or a match with compare register 0. ? the counter value can be initialized to 0000h upon a reset, software clear, or match with compare register 0. b : output compare ( 2 channels per one module ) the output compare module consists of two 16-bit compare registers, compare output latch, and control register. when the 16-bit free-running timer value matches the compare register value, the output level is reversed and an interrupt is issued. ? the two compare registers can be used independently. output pins and interrupt flags corresponding to compare registers ? output pins can be controlled based on pairs of the two compare registers. output pins can be reversed by using the two compare registers. ? initial values for output pins can be set. ? interrupts can be generated upon a compare match. c : input capture ( 2 channels per one module ) the input capture module consists of two 16-bit capture registers and control registers corresponding to two independent external input pins. the 16-bit free-running timer value can be stored in the capture register and an interrupt is issued simultaneously upon detection of an edge of a signal input from an external input pin. ? the detection edge of an external input signal can be specified. rising, falling, or both edges ? two input channels can operate independently. ? an interrupt can be issued upon a valid edge of an external input signal.
mb91360g series 140 (2) registers (3) block diagram a : 16 - bit free - running timer b : 16 - bit output compare c : 16 - bit input capture tcdt tccs timer data register timer status register 15 0 0000cb h 0000c8 h occp0/1 ocs0 ocs1 compare register control status register 15 0 0000b8 h 0000bc h 0000be h ipc0/1 ics0/1 iotdbl0 capture register disable/control status register 15 0 0000ac h 0000b0 h 0000b2 h tq control logic to each block 16-bit timer compare register 0 bus tq edge selection edge selection out0 clear out1 in0 interrupt 16-bit free-run timer output compare 0 compare register 1 output compare 1 capture register 0 input caputure 0 capture register 1 input caputure 1 in1
mb91360g series 141 22. alarm comparator this section provides an overview of the alarm comparator (also called under/overvoltage detection) , de- scribes the register structure and functions, and describes the operation of the alarm comparator. (1) block diagram (2) registers alarm comparator - analog part umqa02 alarm comparator - digital part alarm out1 pd out2 f-module b-module fr51 b0dx acsr stop stop rst clkp clkp clkp rst rb [15:0] rb [15:0] wrcr pmwr rdcr rsleep cdble irq_ac interrupt logic ck ck av dd dq dq irq_ac cdble reg rsleep dec alarm comparator clock disable register (accdbl) alarm comparator status disable register (acsr) address bits initial value 00000180 h - - - - - - - 0 b ? access address bits initial value 00000181 h -11xxx00 b ? access r/w 76543210 ? ? ? ???? cdble r/w r/w r r r/w r/w r/w 76543210 ov_en ? uv-en out2 out1 irq ien pd
mb91360g series 142 23. power down reset this section provides an overview of the power down reset, and describes the register structure. the power down reset module performs a system reset when v cc goes below a threshold voltage. the reset signal is be disabled and enabled by setting the power down reset control register pdrcr. for low power applications the digital and the analog part of the power down reset control circuit can be disabled. ( 1 ) block diagram (2) register pdcomp in out input stage en rst pdrstx s q r 9-bit lfsr counter ready clr wr rb [1] (rd bit) pdrcr access initial value (init) initial value (rst) ? ? x ? ? x ? ? x ? ? x r/w 0 x r/w 0 x r/w 0 x 76543210 ? ? ? x ???? cdsble pd en
mb91360g series 143 24. serial i/o interface (sio) this section provides an overview of the serial i/o interface (sio) , and describes the register structure. (1) block diagram this block is a serial i/o interface that allows data transfer using clock synchronization. the interface consists of a single eight-bit channel. data can be transferred from the lsb or msb. mb91360g series contains two serial i/o units sio0 and sio1. this section only describes sio0. please see the io-map for the register addresses of sio1. the serial i/o interface operates in two modes : ? internal shift clock mode : data is transferred in synchronization with the internal clock. ? external shift clock mode : data is transferred in synchronization with the clock supplied via the external pin (sck) . by manipulating the general-purpose port sharing the external pin (sck) , data can also be transferred by a cpu instruc tion in this mode. interrupt request sin3 (msb first) d7 to d0 d7 to d0 (lsb first) read write transfer direction selection sot3 sck3 internal clock 10 2 smd2 smd1 smd0 sir sie busy stop strt mode bds ? scoe internal data bus sdr (serial data register) control circuit shift clock counter internal data bus
mb91360g series 144 ( 2 ) registers serial mode control status register (smcs) sio edge selection/clock disable register (ses) serial data register (sdr) address : 000084 h address : 000085 h address : 000086 h address : 000087 h 15 14 13 12 11 10 9 8 smd1 smd2 smd0 sie sir busy stop strt 76543210 ? ??? mode bds ? scoe 15 14 13 12 11 10 9 8 ? ????? dbl neg 76543210 d6 d7 d5 d4 d3 d2 d1 d0
mb91360g series 145 25. sound generator this section provides an overview of the sound generator, and describes the register structure. the sound generator consists of the sound control register, frequency data register, amplitude data register, decrement grade register, tone count register, sound disable register, pwm pulse generator, frequency counter, decrement counter and tone pulse counter. (1) registers sound control register (sgcr) frequency data register (sgfr) amplitude data register (sgar) decrement grade register (sgdr) tone count register (sgtr) sound disable register (sgdbl) bit no. address : 0000ef h read/write default value bit no. address : 0000ee h read/write default value bit no. address : 0000f1 h read/write default value bit no. address : 0000f0 h read/write default value bit no. address : 0000f3 h read/write default value bit no. address : 0000f2 h read/write default value bit no. address : 0000ed h read/write default value (r/w) ( 0 ) (r/w) ( 0 ) ( ? ) ( ? ) ( ? ) ( ? ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) 76543210 s0 (r/w) ( 0 ) s1 tone ?? inte int st ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( r ) ( 0 ) (r/w) ( 0 ) 15 14 13 12 11 10 9 8 ? (r/w) ( 0 ) tst ???? busy dec (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) 76543210 d6 (r/w) ( x ) d7 d5 d4 d3 d2 d1 d0 (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) 15 14 13 12 11 10 9 8 d6 (r/w) ( 0 ) d7 d5 d4 d3 d2 d1 d0 (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) 76543210 d6 (r/w) ( x ) d7 d5 d4 d3 d2 d1 d0 (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) 15 14 13 12 11 10 9 8 (r/w) ( x ) d6 d7 d5 d4 d3 d2 d1 d0 ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) (r/w) ( 0 ) 76543210 ? ( ? ) ( ? ) ? ? ???? dbl
mb91360g series 146 (2) block diagram s1 s0 tone inte int st 1/d dec co en pwm ci dec ci co en ci co en co en d en q sga sgo irq clock input prescaler 8-bit pwm pulse generator frequency counter toggle flip-flop reload reload amplitude data register decrement grade register decrement counter decrement grade register mix tone pulse counter tone count register
mb91360g series 147 26. stepper motor controller this section provides an overview of the stepper motor control module, and describe the register structure. the stepping motor controller consists of two pwm pulse generators, four motor drivers, selector logic and the zero rotor position detector. the four motor drivers have high output drive capabilities and they can be directly connected to the four ends of two motor coils. the combination of the pwm pulse generators and selector logic is designed to control the rotation of the motor. a synchronization mechanism assures the synchronous operations of the two pwms. the zero rotor position detector helps cpu obtain feed back information of the rotor movements. the following sections describe the stepping motor controller 0 only. the other controllers have the same functions. the register addresses are found in the i/o map. note : the rotor zero position detection capability is protected by a patent from siemens vdo automatic ag and may only be used with vdos prior approval. (1) block diagram p1 p0 pwm1p0 pwm2p0 pwm1m0 pwm2m0 pwm2m0 comparator zero rotor position detector power down ce ck en ck en pwm pwm bs debounce logic 8-bit counter 1/9 av cc reference voltage machine clock prescaler pwm1 pulse generator selector pwm1 compare register pwm1 selector register pwm2 pulse generator selector load pwm2 compare register pwm2 select register - + zero detect 0 register
mb91360g series 148 (2) registers pwm control 0 register (pwc0) zero detect 0 register (zpd0) pwm1 compare 0 register (pwc10) pwm2 compare 0 register (pwc20) pwm1 select register (pws10) pwm2 select register (pws20) pwm clock disable register (smdbl0) bit no. address : 0000d1 h read/write default value bit no. address : 0000d0 h read/write default value bit no. address : 0000d9 h read/write default value bit no. address : 0000d8 h read/write default value bit no. address : 0000db h read/write default value bit no. address : 0000da h read/write default value bit no. address : 0000e8 h read/write default value ( ? ) ( ? ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) ( ? ) ( ? ) ( ? ) ( ? ) (r/w) ( 0 ) 76543210 ? ( ? ) ( ? ) ? p1 p0 ce ?? tst (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 1 ) (r/w) ( 0 ) 15 14 13 12 11 10 9 8 s0 (r/w) ( 0 ) s1 ts t2 t1 t0 pd rs (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) 76543210 d6 (r/w) ( x ) d7 d5 d4 d3 d2 d1 d0 (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) 15 14 13 12 11 10 9 8 d6 (r/w) ( x ) d7 d5 d4 d3 d2 d1 d0 ( ? ) ( ? ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) 76543210 ? ( ? ) ( ? ) ? p2 p1 p0 m2 m1 m0 (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) 15 14 13 12 11 10 9 8 bs ( ? ) ( ? ) ? p2 p1 p0 m2 m1 m0 ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) (r/w) ( 0 ) 76543210 ? ( ? ) ( ? ) ? ? ???? dbl
mb91360g series 149 27. real time clock this section provides an overview of the real time clock (also called watchtimer) , describes the register structure and functions.the real time clock (watch timer) consists of the timer control register, sub-second register, second/minute/hour registers, 1/2 clock divider, 21bit prescaler and second/minute/hour counters. the real time clock operates as the real-world timer and provides the real-world time information. (1) block diagram inte0 int0 en ci en load co co wot irq co co inte1 st updt int1 inte2 int2 int3 int3 oscillation clock 1/2 clock divider 21 bit prescaler sub second register second counter minute counter hour counter 6 bits 6 bits 5 bits second/minute/hour register
mb91360g series 150 (2) registers (continued) timer disable register (wtdbl) timer control register (wtcr) sub-second register (wtbr) second register (wtsr) bit no. address : 0000f5 h read/write default value bit no. address : 0000f7 h read/write default value bit no. address : 0000f6 h read/write default value bit no. address : 0000fb h read/write default value bit no. address : 0000fa h read/write default value bit no. address : 0000f9 h read/write default value bit no. address : 0000fe h read/write default value ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) ( ? ) (r/w) ( 0 ) 76543210 ? ( ? ) ( ? ) ? ? ???? dbl (r/w) ( 0 ) (r/w) ( 0 ) ( ? ) ( ? ) ( r ) ( 0 ) (r/w) ( 0 ) ( ? ) ( ? ) (r/w) ( 0 ) 76543210 tst1 (r/w) ( 0 ) tst2 tst0 ? run updt ? st (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) 15 14 13 12 11 10 9 8 int3 (r/w) ( 0 ) inte3 inte2 int2 inte1 int1 inte0 int0 (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) 76543210 d6 (r/w) ( x ) d7 d5 d4 d3 d2 d1 d0 (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) 15 14 13 12 11 10 9 8 d14 (r/w) ( x ) d15 d13 d12 d11 d10 d9 d8 ( ? ) ( ? ) ( ? ) ( ? ) (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) 76543210 ? ( ? ) ( ? ) ?? d20 d19 d18 d17 d16 ( ? ) ( ? ) (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) 15 14 13 12 11 10 9 8 ? ( ? ) ( ? ) ? s5 s4 s3 s2 s1 s0
mb91360g series 151 (continued) minute register (wtmr) hour register (wthr) bit no. address : 0000fd h read/write default value bit no. address : 0000fc h read/write default value ( ? ) ( ? ) (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) 76543210 ? ( ? ) ( ? ) ? m5 m4 m3 m2 m1 m0 ( ? ) ( ? ) ( ? ) ( ? ) (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) (r/w) ( x ) 15 14 13 12 11 10 9 8 ? ( ? ) ( ? ) ?? h4 h3 h2 h1 h0
mb91360g series 152 28. subclock the subclock system provides various power saving modes. the key of the concept is to supply the 32 khz clock signal only to the real time clock rtc) module, while the rest of the mcu is provided with 4 mhz clock signal in order to achieve lower power supply current in the rtc32k mode. this behavior can be altered by the configuration input, selclk pin to switch the rtc module to operate with the 4 mhz clock. the following sections describe the operation with selclk connected to 0 and selclk connected to 1 respectively. note : on mb91f361ga and mb91f362ga selclk should always be connected to 1, subclock operation is not implemented on those devices. (1) operation of subclock (selclk = = = = 0) the next table summarizes the operation states of the components related to the subclock system.to simplify this table sleep modes are not listed but the operation is the same as for run modes except that the cpu is stopped. the following table summarizes those operation modes and necessary software settings. it is recommended that pll2en is set to 1 after the initialization to start the 32 khz oscillation and this bit should be kept at 1 during the operation. otherwise the 32 khz oscillator does not start. also bits 9 and 10 of the clkr register (address 0046h) should always be set to 0 during operation. mode power dissipation operation of components 4 m osc. 32 k osc. rtc cpu & peripheral pll run high run run run run stop/run rtc4m32k medium low run run run stop stop rtc32k low stop run run stop stop stop lowest stop stop stop stop stop mode software setting stop pll1en pll2en oscd1 oscd2 rtc32 run 0 0 or 1 1 dont care dont care dont care rtc4m32k 1 dont care 1 0 0 dont care rtc32k 1 dont care 1 1 0 1 stop 1 dont care dont care 1 1 dont care
mb91360g series 153 (2) 4 mhz real time clock configuration (selclk = = = = 1) when the selclk pad is connected logic level 1, the 32 khz oscillation is disabled regardless of the software setting. in this configuration, the real time clock module is supplied with the 4 mhz oscillation clock signal. the following table summaries the modes available in this configuration. (3) use of real time clock module there is some additional consideration needed to operate the rtc module to achieve the desired functionality. because the rtc module is directly connected to the 32 khz oscillation clock, the oscillation stabilization time has to be taken care of by the software.this can be achieved by using another timer (e.g the time base timer) to trigger the software to start the rtc module (setting of st bit to 1) . it is also important to stop the rtc module before entering the stop mode. otherwise, the reactivation from stop mode results in unpredictable operation of the rtc module. after the reactivation, the oscillation stabilization time has to be measured again by the software, then the rtc module can be restarted. mode power dissipation operation of components 4 m osc. 32 k osc. rtc cpu & peripheral pll run high run stop run run stop/run rtc4m medium low run stop run stop stop stop lowest stop stop stop stop stop mode software setting stop pll1en pll2en oscd1 oscd2 rtc32 run 0 0 or 1 dont care dont care dont care dont care rtc4m 1 dont care dont care 0 dont care dont care stop 1 dont care dont care 1 dont care dont care
mb91360g series 154 29. 32 khz clock calibration unit the 32 khz clock calibration module provides possibilities to calibrate the 32 khz oscillation clock with respect to the 4 mhz oscillation clock. (1) description this hardware allows the software to measure time generated by the 32 khz clock with the 4 mhz clock. by utilizing this hardware in conjunction with software processing, the accuracy of the 32 khz clock can come closer to that of the 4 mhz clock. the measurement result from the 32 khz clock calibration module can be processed by the software and the setting required for the real time clock module can be obtained. this module consists of two timers, one operating with the 32 khz clock and the other operating with the 4 mhz clock. the 32 khz timer triggers the 4 mhz timer and resulting 4 mhz timer value is stored in a register. the value stored in this register can be used for the subsequent software processing to calculate the desired real time clock modules setting. (2) block diagram uc18clk gate gate gate gate sync clkp 3 32 strt ready runs strt rsleepb rsleepb strt slkpg2 = clkp | ( ~ strt & rsleepb) ; osc4 osc32 clkp rb rsleep rmw int *_rd *_wr rst async rst strt strts strt ready run uc18trd uc18trr cutr counter (16 bit) cutr (24 bit) strt cutd clk32g rb clkpg clk4g = osc4 | ~ strt | (ready & - runs) ; clk4g clkpg2 32 khz timer 4 mhz timer anync rst sync 32 3 4 run & runs sync 4 3 clkp ready runss1 runss & reset ready- pulse cucr (3 bit) cutr (24 bit) cutd (16 bit) cutd vc18rbi fc18 reset set strt set /reset set /reset inten int uc18bus uc18io int_i int_int *_rdb *_wrb rstb & rbb rsleepb rmwb
mb91360g series 155 (3) timing 32 khz strt (clkp) strts (32 khz) run (32 khz) runs (4 mhz) 32 khz counter (16 bit) 4 mhz counter (24 bit) ready (32 khz) readypulse (clkp) int (clkp) new cutr old cutr cutd cutd cutd-1 2 1 0 0
mb91360g series 156 (4) clocks the module operates with 3 different clocks : the 4 mhz clock osc4, the 32 khz clock osc32 and the rbus clock clkp. synchronization circuits adapt the different domains. all 3 clocks are gated. the 32 khz and the 4 mhz clock are switched off if strt is 0. clkpg is gated by rsleep and clkpg2 by rsleep and strt for the 2 bits, which are set/reset by hardware. the clock frequencies have to fulfill the following requirements : 1.) clock ratio t osc32 > 2 t osc4 + 3 t clkp t osc4 < 1 / 2 t osc32 - 3 / 2 t clkp t clkp < 1 / 3 t osc32 - 2 / 3 t osc4 2.) the input frequencies must not exceed the values given in next table. maximum operation frequencies examples of valid clock ratios which fulfill requirements 1 and 2 clkp osc32 osc4 maximum 32 mhz 31.25 ns 4 mhz 250 ns 13 mhz 76.9 ns osc32 osc4 clkp maximum operation speed 4 mhz 250 ns 13 mhz 76.9 ns 32 mhz 31.25 ns standard tdir mode 500 khz 2000 ns 4 mhz 250 ns 4 mhz 250 ns normal operation 32 khz 31.25 us 4 mhz 250 ns > 2 mhz 500 ns
mb91360g series 157 (5) register description a : calibration unit control register (cucr) control register low byte (cucrl) b : 32 khz timer data register ( cutd ) 32 khz timer data register high byte (cutdh) 32 khz timer data register low byte (cutdl) c : 4 mhz timer data register (cutr) 4 mhz timer data register1 high byte (cutr1h) 4 mhz timer data register1 low byte (cutr1l) 4 mhz timer data register2 high byte (cutr2h) 4 mhz timer data register2 low byte (cutr2l) bit no. address : 000191 h read/write default value bit no. address : 000192 h read/write default value bit no. address : 000193 h read/write default value bit no. address : 000194 h read/write default value bit no. address : 000195 h read/write default value bit no. address : 000196 h read/write default value bit no. address : 000197 h read/write default value ( r ) ( 0 ) ( r ) ( 0 ) (r/w) ( 0 ) ( r ) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) 76543210 ? ( r ) ( 0 ) ?? strt ?? int inten (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) 15 14 13 12 11 10 9 8 tdd14 (r/w) ( 1 ) tdd15 tdd13 tdd12 tdd11 tdd10 tdd9 tdd8 (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) (r/w) ( 0 ) 76543210 tdd6 (r/w) ( 0 ) tdd7 tdd5 tdd4 tdd3 tdd2 tdd1 tdd0 ( r ) ( 0 ) ( r ) ( 0 ) ( r ) ( 0 ) ( r ) ( 0 ) ( r ) ( 0 ) ( r ) ( 0 ) ( r ) ( 0 ) 15 14 13 12 11 10 9 8 ? ( r ) ( 0 ) ? ? ????? ( r ) ( 0 ) ( r ) ( 0 ) ( r ) ( 0 ) ( r ) ( 0 ) ( r ) ( 0 ) ( r ) ( 0 ) ( r ) ( 0 ) 76543210 tdr22 ( r ) ( 0 ) tdr23 tdr21 tdr20 td19 tdr18 tdr17 tdr16 ( r ) ( 0 ) ( r ) ( 0 ) ( r ) ( 0 ) ( r ) ( 0 ) ( r ) ( 0 ) ( r ) ( 0 ) ( r ) ( 0 ) 15 14 13 12 11 10 9 8 tdr14 ( r ) ( 0 ) tdr15 tdr13 tdr12 tdr11 tdr10 tdr9 tdr8 ( r ) ( 0 ) ( r ) ( 0 ) ( r ) ( 0 ) ( r ) ( 0 ) ( r ) ( 0 ) ( r ) ( 0 ) ( r ) ( 0 ) 76543210 tdr6 ( r ) ( 0 ) tdr7 tdr5 tdr4 td3 tdr2 tdr1 tdr0
mb91360g series 158 30. flash memory mb91360g series devices feature 512 k of embedded flash memory unit derived from the mb29lv400c and the flash memory interface circuit. (1) out line of flash memory the flash memory consists of a flash memory unit derived from the mbm29lv400c and a flash memory interface circuit. flash memory : ? 512 kword 8 bit/256 kword 16 bit/128 kword 32 bit (64 kbyte 3 + 32 kbyte + 8 kbyte 2 + 16 kbyte) sectors ? uses automatic program algorithm (embedded algorithm ? ) ? erase pause/restart function ? detects completion of writing/erasing using data polling or toggle bit functions ? detects completion of writing/erasing by ry/by pin ? compatible with jedec standard commands ? performs minimum of 10,000 write/erase operations ? sector erase function (any combination of sectors) ? sector protect function ? temporary sector protect cancellation function ? allows flash memory interface circuit to write to/erase flash memory both under control of external pin by writer and under control of internal bus by cpu. embedded algorithm ? is a registered trademark of advanced micro devices, inc.
mb91360g series 159 (2) block diagrams of flash memory a : block diagram of flash memory figure shows the block diagram of the flash memory unit, which has almost the same configuration as the mbm29lv400c. b : entire block diagram of flash memory figure shows the entire block diagram of the flash memory with the flash memory interface circuit. we ry/by buffer ce a0 to a17 a-1 oe byte reset ry/by erase circuit write circuit control circuit chip enable/ output enable circuit i/o buffer data latch y gate y decoder cell matrix x decoder address latch stb stb dq 0 to dq 15 low v cc detection circuit write/erase pulse timer user logic bus ext.bus i/f flash memorry interface circuit 4 mbit flash memory byte ce oe we a0 to a18 dq0 to dq15 ry/by byte ce oe we a0 to a17 a-1 dq0 to dq15 ry/by reset external reset signal ry/by write enable signal
mb91360g series 160 c : sector configuration i) write, byte read, half word read ii ) long word read flash memory mode other modes 8 bit 2 7ffff h fffff h sector 13 16 kb 7c000 h fc000 h sector 12 8 kb 7a000 h fa000 h sector 11 8 kb 78000 h f8000 h sector 10 32 kb 70000 h f0000 h sector 9 64 kb 60000 h e0000 h sector 8 64 kb 50000 h d0000 h sector 7 64 kb 40000 h c0000 h sector 6 16 kb 3c000 h bc000 h sector 5 8 kb 3a000 h ba000 h sector4 8 kb 38000 h b8000 h sector 3 32 kb 30000 h b0000 h sector 2 64 kb 20000 h a0000 h sector 1 64 kb 10000 h 90000 h sector 0 64 kb 00000 h 80000 h msb lsb flash memory mode other modes 8 bit 2 8 bit 2 7ffff h fffff h sector 13 16 kb sector 6 16 kb 78000 h f8000 h sector 12 8 kb sector 5 8 kb 74000 h f4000 h sector 11 8 kb sector 4 8 kb 70000 h f0000 h sector 10 32 kb sector 3 32 kb 60000 h e0000 h sector 9 64 kb sector 2 64 kb 40000 h c0000 h sector 8 64 kb sector 1 64 kb 20000 h a0000 h sector 7 64 kb sector 0 64 kb 00000 h 80000 h
mb91360g series 161 (3) write/erase modes the flash memory can be accessed in two different ways; the flash memory mode allowing write/erase directly from the external pins, and the other modes allowing write/erase from the cpu via the internal bus. these modes are selected by the external mode pins. a : flash memory mode the cpu stops when the mode pins are set to 111 while the initx signal is asserted. the flash memory interface circuit is directly connected to the external bus interface, allowing direct control by the external pins. this mode makes the mcu seem like a standard flash memory at the external pins, and write/erase can be performed using a flash memory programmer. in the flash memory mode all the operations supported by the flash memory automatic algorithm can be used. b : other modes the flash memory is located in the cs1x area of the cpu memory space and like ordinary mask rom can be read-accessed and program-accessed from the cpu through the flash memory interface circuit. writing/erasing the flash memory is performed by instructions from the cpu via the flash memory interface circuit. therefore, this mode allows rewriting even when the mcu is soldered on the target board. the sector protect operations can not be performed in these modes. c : control signals of flash memory next table lists the flash memory control signals in the flash memory mode. there is almost a one-to-one correspondence between the flash memory control signals and the external pins of the mbm291v400ta. the v id (12 v) pins required by the sector protect operations are md0, md1 and md2 instead of a9, reset and oe for the mbm29lv400c. in the flash memory mode, the width of the external data bus can be 8 or 16 bit.
mb91360g series 162 flash control signals mb91f362ga pins used in flash memory mode a19, a20 should be pulled up, init x must be low during power on for at least 500 ns. pins not used in flash memory mode mb91f362ga mbm29lv400c notes pin number normal function flash memory mode 1 to 8 d24 to d31 d24 to d31 dq8 to dq15 9a0 a0 a-1 10 to 24 a1 to a15 a1 to a15 a0 to a14 27 to 30 a16 to a18 a16 to a18 a15 to a17 32 cs4x cs4x we 33 cs5x cs5x byte 35 rdy rdy oe 36 bgrntx bgrntx ce 37 brq brq ry/by 111 md0 vda9 a9 (v id ) 112 md1 vdrs reset (v id ) 113 md2 vdoe oe (v id ) 115 initx initx reset 201 to 208 d16 to d23 d16 to d23 dq0 to dq7 183 to 197, 200 d0 to d15 output when reading from flash ? pull up 34 cs6x tmodex ? must be pulled up 30 to 31 a19 to a20 a19 to a20 ? pull up or pull down mb91f362ga notes pin number normal function pin state 75 to 76 da0, da1 output leave open 77 alarm input pull down 81 to 83 testx, cputestx, ltestx input pull up or leave open (internal pull-up) 114 hstx input pull up or leave open (internal pull-up) 116 monclk output leave open 117 selclk input pull up 119, 121 x0, x0a input pull down 120, 122 x1, x1a output leave open 124 cpo output leave open 125 vci input pull down all other signals input pull up
mb91360g series 163 mb91fv360ga (continued) mb91fv360ga mbm29lv400c pin number normal function flash memory mode 202 a0 a0 a-1 310 a1 a1 a0 201 a2 a2 a1 357 a3 a3 a2 257 a4 a4 a3 144 a5 a5 a4 309 a6 a6 a5 256 a7 a7 a6 200 a8 a8 a7 356 a9 a9 a8 308 a10 a10 a9 92 a11 a11 a10 44 a12 a12 a11 255 a13 a13 a12 143 a14 a14 a13 199 a15 a15 a14 307 a16 a16 a15 91 a17 a17 a16 142 a18 a18 a17 140 cs4x cs4x we 196 cs5x cs5x byte 89 cs6x tmodx ? 305 rdy rdy oe 139 bgrntx bgrntx ce 88 brq brq ry/by 293 md0 vda9 a9 (v id ) 31 md1 vdrs reset (v id ) 239 md2 vdoe oe (v id ) 30 initx initx reset 46 d16 d16 dq0 95 d17 d17 dq1 1d18 d18dq2 148 d19 d19 dq3 205 d20 d20 dq4
mb91360g series 164 (continued) mb91f369ga a. pin 70 must be pulled high in flash memory mode. b. pins 74 and 75 must be pulled low in flash memory mode. c. functionality as described in the data sheet of mbm29lv400c. avrh must be tight to a high level, alarm to a low level. all other pins can be left open during flash memory mode. mb91fv360ga mbm29lv400c pin number normal function flash memory mode 45 d21 d21 dq5 94 d22 d22 dq6 260 d23 d23 dq7 312 d24 d24 dq8 204 d25 d25 dq9 147 d26 d26 dq10 93 d27 d27 dq11 259 d28 d28 dq12 203 d29 d29 dq13 146 d30 d30 dq14 258 d31 d31 dq15 mb91f369ga mbm29lv400c pin number normal function flash memory mode function in flash memory mode 58 md0 hvda9 high volt. a9 (c) a9 (v id ) 59 md1 hvdr5 high volt. reset (c) reset (v id ) 60 md2 hvdoe high volt. oe (c) oe ( v id ) 62 intx rstx hardware reset reset 68 int0 ry/byx ready/busy ry/by 69 int1 cex chip enable ce 70 int2 tstx (a) flash test 71 int3 bytex switch 8/16 bit mode byte 72 int4 wex write enable we 73 int5 oex output enable oe 74 int6 atdin (b) access signal atd 75 int7 eqin (b) access signal eq 121 to 136 d0 to d15 aq19 downto aq4 address input a19 downto a4 139 to 154 d16 to d31 dq16 to dq31 data input/output dq0 to dq15 157 to 160 a0 to a3 aq0 to aq3 address input a0 to a3
mb91360g series 165 (4) flash control status register (fmcs) flash memory macros used in devices : normal flash macro used in : mb91f362ga fast flash macro used in : mb91fv360ga *: it is not allowed to use rdyeg. address fv360ga, f362ga : 00007000 h access initial value value after boot rom r/w 1 1 r/w 1 1 r 0 0 r x x r/w 0 0 r/w 0 0 r/w 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ? r/w 1 0 faccen ? rdyeg* rdy rdyi we lpm
mb91360g series 166 (5) read/write access in the flash memory mode, read/write access to the flash memory must be under control of the external pins. however, with the cpu access, there are no special timing constraints on read/write access because the flash memory is controlled by the flash memory interface circuit. in this section, write access does not directly mean program flash memory. it implies activation of the flash commands. a : read / write access in flash memory mode next table gives the setting of pins for read/write access in the flash memory mode. there is no special problem with control of these pins if connected to a flash memory writer. however, in other cases, timing specifications must be met. setting conditions of pins for read/write access in flash memory mode note : this table uses pin names from f362ga. check corresponding pin names of other devices. b : read access with cpu operations bgrntx (ce ) rdy (oe ) cs4x (we ) a0 to a18 d16 to d31 init read l l h read address d out h write l h l write address d in h output disable l h h x high-z h standby h x x x high-z h hardware reset x x x x high-z l flash wait control register ( fmwt ) address 00007004 h access initial value value after boot rom normal flash macro value after boot rom fast flash macro r/w 0 0 0 r/w 0 0 0 r/w 0 0 1 r/w 0 0 0 r/w 0 0 0 r/w 1 1 1 r/w 1 1 1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ? ? fac1 fac0 eqinh wtc2 wtc1 wtc0
mb91360g series 167 normal flash macro : recommended settings without applying clock modulation when applying clock modulation example for flash memory read access with 1 cycle for the low time of facc and 3 wait cycles the minimum value for t fp is 15 ns, for t facc it is 40 ns. clkb unmodulated core clock frequency [mhz] fac1 fac0 eqinh wtc2 wtc1 wtc0 facc low cycles/wait cycles fmwt 64 010011 1 / 313 h 48 010011 1 / 313 h 40 010010 1 / 212 h 32 000010 0.5 / 202 h 24 000001 0.5 / 101 h 16 000001 0.5 / 101 h clkb core clock frequency [mhz] peak max frequency fac1 fac0 eqinh wtc2 wtc1 wtc0 facc low cycles/wait cycles fmwt 48 64 010011 1 / 313 h 32 48 010011 1 / 313 h 24 40 010010 1 / 212 h 24 32 000010 0.5 / 202 h 16 24 000001 0.5 / 101 h a1 a2 a3 d1 clkb fa fwaitr facc fd 3 wait cycles 1 cycle facc = "l" t fp t facc core clock f-bus address f-bus wait facc for flash f-bus data
mb91360g series 168 fast flash macro : recommended settings without applying clock modulation when applying clock modulation example for flash memory read access with 1 cycle for the high time of atdin and 3 wait cycles the minimum value for t watd is 10 ns, the minimum value for t weq is 20 ns. the minimum value for t rc is 40 ns. the maximum value for t acc is t watd + t weq + 5 ns. clkb unmodulated core clock frequency [mhz] fac1 fac0 eqinh wtc2 wtc1 wtc0 atdin high cycles/wait cycles fmwt 64 010011 1 / 313 h 48 000010 0.5 / 202 h 40 000010 0.5 / 202 h 32 001001 0.5 / 109 h 24 000001 0.5 / 101 h 16 000001 0.5 / 101 h clkb core clock frequency [mhz] peak max frequency fac1 fac0 eqinh wtc2 wtc1 wtc0 at d i n h i g h cycles/wait cycles fmwt 48 64 0 1 0 0 1 1 1 / 313 h 32 48 0 0 0 0 1 0 0.5 / 202 h 24 40 0 0 0 0 1 0 0.5 / 212 h 24 32 0 0 1 0 0 1 0.5 / 109 h 16 24 0 0 0 0 0 1 0.5 / 101 h 3 wait cycles 1 cycle atdin ="h" a1 d1 a2 a3 t watd t weq core clock f-bus address f-bus wait atdin for flash eqin for flash f-bus data t acc t rc clkb fa fwaitr atdin eqin fd
mb91360g series 169 c : write access with cpu recommended settings for wtc2 to wtc0 for write access to the flash memory, faccen of fmcs should be set to 1 for writing, so fac1, fac0, eqinh register settings then have no meaning for the write operation without applying clock modulation when applying clock modulation clkb unmodulated core clock frequency [mhz] wtc2 wtc1 wtc0 wait cycles fmwt 64 setting not allowed for writing 48 100 4 x4 h 40 100 4 x4 h 32 010 2 x2 h 24 010 2 x2 h 16 001 1 x1 h clkb core clock frequency [mhz] peak max frequency wtc2 wtc1 wtc0 wait cycles fmwt 48 64 setting not allowed for writing 32 48 1 0 0 4 x4 h 24 40 1 0 0 4 x4 h 24 32 0 1 0 2 x2 h 16 24 0 1 0 2 x2 h
mb91360g series 170 (6) automatic write/erase irrespective of the flash memory mode or other modes, writing to/erasing the flash memory unit is performed by starting the flash memory automatic algorithm. to start the automatic algorithm, various sequences of write accesses are executed in 1 to 6 cycles. they are called flash commands. a : flash commands there are four commands for starting the automatic algorithm of the flash memory unit; read/reset, write, chip erase, and sector erase. there are also erase suspend and erase resume commands for the sector erase operation. next tables give the command sequence lists in the flash memory and other modes. b : command sequence command sequence list (cpu access) addresses in the table are the values in the cpu memory space. all addresses and data are hexadecimal values, where x is any value and ** may be 08 to 0f. * : two read/reset commands reset flash memory to the read mode. command sequence write cycle of bus write cycle of first bus write cycle of second bus write cycle of third bus read/ write cycle of fourth bus write cycle of fifth bus write cycle of sixth bus ad- dress data ad- dress data ad- dress data ad- dress data ad- dress data ad- dress data read/ reset* 1 **xxxx xxf0 ? ????????? read/ reset* 4 **5554 xxaa **aaa8 xx55 **5554 xxf0 ra rd ???? write 4 **5554 xxaa **aaa8 xx55 **5554 xxa0 pa (even) pd (half word) ???? chip erase 6 **5554 xxaa * * aaa8 xx55 **5554 xx80 **5554 xxaa **aaa8 xx55 **5554 xx10 sector erase 6 **5554 xxaa **aaa8 xx55 **5554 xx80 **5554 xxaa **aaa8 xx55 sa (even) xx30 sector erase suspend input of address ** xxxx or data (xxb0 h ) suspends sector erasing. sector erase resume input of address ** xxxx or data (xx30 h ) suspends and resumes sector erasing.
mb91360g series 171 command sequence list (flash memory mode) addresses in the table are values for writer addresses. all addresses and data are hexadecimal values, where x is any value and * may be 0 to 7. ra : read address pa : write address. only even addresses can be specified. sa : sector address (see next table) . only even addresses can be specified. rd : read data pd : write data. only word data can be specified. command sequence write cycle of bus write cycle of first bus write cycle of second bus write cycle of third bus read/ write cycle of fourth bus write cycle of fifth bus write cycle of sixth bus ad- dress data ad- dress data ad- dress data ad- dress data ad- dress data ad- dress data read/ reset* 1 * xxxx f0 ?????????? read/ reset* 4 *aaaa aa *5554 55 *aaaa f0 ra rd ???? write 4 * aaaa aa *5554 55 * aaaa a0 pa (even) pd (word) ???? chip erase 6 * aaaa aa *5554 55 * aaaa 80 * aaaa aa *5554 55 * aaaa 10 sector erase 6 *aaaa aa *5554 55 *aaaa 80 *aaaa aa *5554 55 sa (even) 30 sector erase suspend input of address *xxxx or data (b0 h ) suspends sector erasing. sector erase resume input of address *xxxx or data (30 h ) suspends and resumes sector erasing.
mb91360g series 172 sector address for half word mode sector a18 a17 a16 a15 a14 a13 address range sa1311111 ? 7c000 h to 7ffff h sa121111017a000 h to 7bfff h sa11111100 78000 h to 79fff sa10 1 1 1 0 ?? 70000 h to 77fff h sa9 1 1 0 ??? 60000 h to 6ffff h sa8 1 0 1 ??? 50000 h to 5ffff h sa7 1 0 0 ??? 40000 h to 4ffff h sa601111 ? 3c000 h to 3ffff h sa50111013a000 h to 3bfff h sa4011100 38000 h to 39fff h sa3 0 1 1 0 ?? 30000 h to 37fff h sa2 0 1 0 ??? 20000 h to 2ffff h sa1 0 0 1 ??? 10000 h to 1ffff h sa0 0 0 0 ??? 00000 h to 0ffff h
mb91360g series 173 (7) connection to flash memory the flash memory mode of the mb91360g series devices is intended mainly for external connection to a flash memory writer. as indicated in table flash control signals, there is a slight difference between the external pins of the mb91360g series devices and the mbm29lv400c (4 mbit flash memory) . connection to an mbm29lv400c writer requires the socket adapter. flash writer mb91f362ga mb91fv360ga 2.2 k w 2.2 k w 2.2 k w 2.2 k w 2.2 k w 2.2 k w socket adapter a9 reset oe a10 initx rdy md0 md1 md2 mb91f369ga d9 initx int5 md0 md1 md2
mb91360g series 174 (8) notes to use of flash memory notes on the flash memory in mb91360g series devices are given below. a : input of hardware reset (initx) to input a hardware reset when the automatic algorithm is not started, where reading is in progress, a minimum of 500 ns should be taken at a low-level width. in this case, a maximum of 500 ns is required until data can be read from the flash memory after a hardware reset has been activated. similarly, to input a hardware reset when the automatic algorithm is activated, where writing/erasing is in progress, a minimum of 50 ns should be taken in a low-level width. in this case, 20 m s are required until data can be read after the executing operation has been terminated to initialize the flash memory. a hardware reset during writing undefined data being written. a hardware reset during erasing may make the sector being erased unusable. b : canceling software reset , watchdog timer reset , and hardware standby when writing/erasing the flash memory with the cpu access and if reset conditions occur while the automatic algorithm is active, the cpu may run away. this occurs because these reset conditions cause the automatic algorithm to continue without initializing the flash memory unit, possibly preventing the flash memory unit from entering the read state when the cpu starts the sequence after the reset has been deasserted. these reset conditions should be inhibited during writing/erasing the flash memory. c : program access to flash memory when the automatic algorithm is operating, read access to the flash memory is disabled. with the memory access mode of the cpu set to the internal rom mode, writing/erasing should be started after switching the program area to another area such as ram. in this case, when sectors containing interrupt vectors are erased, interrupt processing cannot be executed. for the same reason, all interrupt sources should be disabled while the automatic algorithm is operating. d : hold function when the cpu accepts a hold request, the write signal we of the flash memory unit may be skewed and many cause erroneous writing/erasing. when the acceptance of a hold request is enabled, ensure that the we bit of the control status register (fmcs) is 0. e : applying v id applying v id required for the sector protect operation should always be started and terminated when the supply voltage is on.
mb91360g series 175 (9) timing diagrams in flash mode each timing diagram for the external pins of the mb91360g series in the flash memory mode is shown below. a : data read by read access b : write data polling read ( we control ) a18 to a0 address stable high-z high-z bgrntx (ce) rdy (oe) cs4x (we) d31 to d16 output defined t rc t ac t oe t df t ce t oh t oeh 120 ns 120 ns 0 50 ns 30 ns 120 ns (toggle) 0 ms (read) a18 to a0 d31 to d16 bgrntx (ce) rdy (oe) cs4x (we) third bus cycle data polling 7aaaa h pa pa t wc t as t ah t rc t whwh1 t wph t wp t ghel t dh t df t oh t oe t cs t ds t ce d out d23 pd a0 h v dd (= 5.0 v) pa : write address pd : write data d23 : reverse output of write data d out : output of write data note : the last two bus cycle sequences out of the four are described.
mb91360g series 176 c : write data polling read ( ce control ) d : chip erase / sector erase command sequence a18 to a0 d31 to d16 bgrntx (ce) rdy (oe) cs4x (we) v dd (= 5.0 v) third bus cycle data polling 7aaaa h pa pa t wc t as t wh t ah t whwh1 t cph t cp t ghel t dh t ws t ds d out d23 pd a0 h pa : write address pd : write data d23 : reverse output of write data d out : output of write data note : the last two bus cycle sequences out of the four are described. a18 to a0 d31 to d16 v dd bgrntx (ce) rdy (oe) cs4x (we) 7aaaa h 75554 h 7aaaa h 7aaaa h 75554 h sa* t as t ah t wp t ds t cs t vcs t dh t wph aa h 55 h 80 h aa h 55 h 10 h /30 h t ghwl note : sa is the sector address at sector erasing. 7aaaa h (or 6aaaa h ) is the address at chip erasing.
mb91360g series 177 e : data polling f : toggle bit g : ry / by timing during writing / erasing t oeh t ch t oe t ce t df t eoe t oh t whwh1 or t whwh2 bgrntx (ce) d31 to d16 d23 d23 = valid data d31 - d16 = invalid d31 - d16 = valid data rdy (oe) cs4x (we) high-z d23 * * : dq7 is valid data (the device terminates automatic operation) . t oeh t oe bgrntx (ce) rdy (oe) cs4x (we) data (d31 to d16) * t oes d22 = toggle d22 = toggle d22 = stop toggling d31 to d16 = valid * * : dq6 stops toggling (the device terminates automatic operation) . bgrntx (ce) cs4x (we) rdy (oe) rising edge of last write pulse t busy writing or erasing
mb91360g series 178 h : initx and ry / by timing i : enable sector protect / verify sector protect t rp t ready brq (ry/by) bgrntx (ce) cs4x (oe) t wpp t vlht t oe t csp t oesp t vlht a18 to a13 md0 (a9(v id )) md2 (oe(v id )) 12 v 5 v 12 v 5 v cs4x (we) rdy (oe) d31 to d16 sax 01 h say a7, a2, and a1 (a7, a2, a1) = (0, 1, 0) sa x : first sector address sa y : next sector address
mb91360g series 179 j : temporary sector protect cancellation sector protect cancellation t vlht write/erase command sequence 5 v 12 v 5 v cs4x (we) brq (ry/by) bgrntx (ce) md1 (reset (v id ))
mb91360g series 180 (10) ac characteristics in flash memory mode the ac specifications for the external pins of the mb91360g series in the flash memory mode are shown below. they apply to the case where the user performs read/write access in the flash memory mode. they are not needed for access in the normal mode and for use of a flash memory writer. the values are subject to change without prior notice. a : read access ac characteristics for read access (under recommended conditions) note : sampled, not 100 % tested. parameter symbol test condi- tions value unit min typ max read cycle time t rc ? 120 ?? ns address access time t acc ce = vil oe = vil ?? 120 ns ce to data output t ce oe = vil ?? 120 ns oe to data output t oe ??? 50 ns ce to output floating t df ??? 30 ns oe to output floating t df ??? 30 ns previous cycle data output hold time t oh ? 0 ?? ns initx pin to return to read mode t ready ??? 20 m s
mb91360g series 181 b : write [write / erase command] access ( we control ) ac characteristics for write access (we control) (under recommended conditions) *1 : the internal preprogramming time before erasing is not included. *2 : applies only to sector protection note : sampled, not 100 % tested. parameter symbol value unit min typ max write cycle time t wc 120 ?? ns address setup time t as 0 ?? ns address hold time t ah 50 ?? ns data setup time t ds 50 ?? ns data hold time t dh 0 ?? ns output enable setup time t oes 0 ?? ns output enable hold time read t oeh 0 ?? ns toggle and data polling 10 ?? ns read recovery time before write t ghwl 0 ?? ns ce setup time t cs 0 ?? ns ce hold time t ch 0 ?? ns write pulse width t wp 50 ?? ns write pulse width high level t wph 20 ?? ns write continuation time t whwh1 ? 8 ?m s sector erase continuation time* 1 t whwh2 ? 115s v cc setup time t vcs 50 ??m s voltage transition time* 2 t vlhl 4 ??m s write pulse width* 2 t wpp 100 ??m s oe setup time for validating we* 2 t oesp 4 ??m s ce setup time for validating we * 2 t csp 4 ??m s init pulse width t rp 500 ?? ns ry/by delay until write/erase is enabled t busy 50 ?? ns
mb91360g series 182 c : write [write / erase command] access ( ce control ) ac characteristics for write access (ce control) (under recommended conditions) * : the internal preprogramming time before erasing is not included. note : sampled, not 100 % tested. parameter symbol value unit min typ max write cycle time t wc 120 ?? ns address setup time t as 0 ?? ns address hold time t ah 50 ?? ns data setup time t ds 50 ?? ns data hold time t dh 0 ?? ns output enable setup time t oes 0 ?? ns output enable hold time read t oeh 0 ?? ns toggle and data polling 10 ?? ns read recovery time before write t ghwl 0 ?? ns we setup time t ws 0 ?? ns we hold time t wh 0 ?? ns ce pulse width t cp 50 ?? ns ce pulse width high level t cph 20 ?? ns write continuation time t whwh1 ? 16 ?m s sector erase continuation time* t whwh2 ? 1.5 30 s v cc setup time t vcs 50 ??m s init pulse width t rp 500 ?? ns ry/by delay until write/erase is enabled t busy 50 ?? ns
mb91360g series 183 n electrical characteristics 1. absolute maximum ratings *1 : making full use of the allowed static dc correct into digital i/o will lead to lower values for v idig min. *2 : applicable to pins : d0 to d31, a0 to a20, cs0x to cs6x, rdy, bgrntx, brq, rdx, wr0x to wr3x, as, ale, clk, dreq0, dack0, deop0, int0 to int7, sgo, sga, sda, scl, sot0, sin0, sck0, ocpa0 to ocpa3, tx0, tx1, rx0, rx1, sot3 to sot4, sin3 to sin4, sck3 to sck4, led0 to led7 (mb91f362ga only) , in0 to in3 (mb91f362ga only) , out0 to out3 (mb91f362ga only) , ocpa4 to ocpa7 (mb91f362ga only) , sot1 to sot2 (mb91f362ga only) , sih1 to sih2 (mb91f362ga only) , sck1 to sck2 (mb91f362ga only) , pwm1p0 to pwm1p3 (mb91f362ga only) , pwm1m0 to pwm1m3 (mb91f362ga only) , pwm2p0 to pwm2p3 (mb91f362ga only) , pwm2m0 to pwm2m3 (mb91f362ga only) use within recommended operating conditions. use at dc voltage (current). the +b signal should always be applied with a limiting resistance placed between the +b signal and the microcontroller. the value of the limiting resistance should be set so that when the +b signal is applied the input current to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods. note that when the microcontroller drive current is low, such as in the power saving modes, the +b input potential may pass through the protective diode and increase the potential at the vcc pin, and this may affect other devices. note that if a +b signal is input when the microcontroller current is off (not fixed at 0 v) , the power supply is provided from the pins, so that incomplete operation may result. note that if the +b input is applied during power-on, the power supply is provided from the pins and the resulting supply voltage may not be sufficient to operate the power-on reset. care must be taken not to leave the +b input pin open. note that analog system input/output pins other than the a/d input pins (lcd drive pins, comparator input pins, etc.) cannot accept +b signal input. (continued) parameter symbol rating unit condition min max digital supply voltage v dd -v ss - 0.3 + 6.0 v stepper motor control supply voltage hv dd -hv ss - 0.3 + 6.5 v storage temperature tstg - 55 + 125 c power consumption p tot ? 2500 mw t a = + 25 c digital input voltage v idig - 0.3* 1 + 5.8 v v ss = 0 v, v dd = 5 v analog input voltage v ia - 0.3 + 5.8 v v ssa = 0 v, v dda = 5 v analog supply voltage v dda -v ssa - 0.3 + 5.8 v v ssa = 0 v analog reference voltage v refh / l - v ssa - 0.3 + 5.8 v v ssa = 0 v static dc current into digital i/o i i/odc - 2.0 + 2.0 ma * 2 static total dc current into digital i/o ?? i i/odc ? ? 20 ma * 2
mb91360g series 184 (continued) sample recommended circuits warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. 2. recommended operating conditions *: this is only valid if the integrated power-down reset circuit is switched-off, else a reset can be triggered at voltages less or equal than 4.5 v (see 23. power down reset) . warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the devices electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol value unit condition min typ max operating temperature t a - 40 + 85 c supply voltage (internal voltage regulator) digital supply v dd - v ss 4.25* 5 5.25 v v ddcore = 3.3 v stepper motor control supply hv dd - hv ss 4.75 5 5.25 v hv ss = 0 v analog supply v dda - v ssa 4.9 5 5.1 v v ssa = 0 v ram data retention voltage v dd - v ss 3.0 ?? v v cc p-ch n-ch r i/o equivalent circuit protective diode limiting resistance + b input (0 v to 16 v)
mb91360g series 185 3. dc characteristics *1 : see 4. run mode current / power consumption . (continued) parameter sym- bol value unit condition min typ max current consump- tion run mode i srun ?? *1 ma t a = 25 c rtc mode i srtc ? 0.5 ? 1.25 500 ma m a f clk = 4 mhz at t a = 25 c f clk = 32 khz at t a = 25 c stop mode i sstop ? 10 200 m af clk = 0 at t a = 25 c stepper motor control h-port output voltage v ohh hv dd - 500 ? hv dd - 125 mv i ol = 30 ma, t c = 25 c v ohl hv ss + 125 ? hv ss + 500 mv i ol = 30 ma, t c = 25 c v ohh hv dd - 500 ? hv dd - 125 mv i ol = 27 ma, t c = 85 c v ohl hv ss + 125 ? hv ss + 500 mv i ol = 27 ma, t c = 85 c v ohh hv dd - 500 ? hv dd - 125 mv i ol = 30 ma, t c = - 40 c v ohl hv ss + 125 ? hv ss + 500 mv i ol = 30 ma, t c = - 40 c smc comparator threshold voltage v thcomp hv dd / 9 - 70 hv dd / 9 hv dd / 9 + 70 mv slew rate ?? 40 ? ns cload = 0 pf alarm comparator threshold voltage over- voltage v tah 4 / 5 v dda - 5 % 4 / 5 v dda 4 / 5 v dda + 5 % v (external 4 : 1 divider) under- voltage v tal 2 / 5 v dda - 5 % 2 / 5 v dda 2 / 5 v dda + 5 % v switching hysteresis v tahys 12.5 25 50 mv alarm sense time t as ?? 10 m s input resistance r in 5 ?? m w at v tah , v tal power down reset threshold voltage v tpor 3.5 4.0 4.5 v switching hysteresis v tpo- rhys 20 50 80 mv reset sense time t rs ?? 10 m s digital outputs output h voltage v oh v dd - 0.5 ? v dd vi load = 4ma output l voltage v ol v ss ? v ss + 0.4 v i load = - 4ma
mb91360g series 186 (continued) *2 : valid for bidirectional tristate i/o pad cell parameter symbol value unit condition min typ max digital inputs* 2 cmos (type : q, s, y, t) high voltage range v ih 0.65 v dd ? v dd v low voltage range v il v ss ? 0.25 v dd v cmos schmitt- trigger (types : e, f, u) high voltage range v ih 0.8 v dd ? v dd v low voltage range v il v ss ? 0.2 v dd v cmos automotive schmitt- trigger (types : a, b, k1, m1, j) high voltage range v ih 0.8 v dd ? v dd v low voltage range v il v ss ? 0.5 v dd v hysteresis voltage ?? 0.5 ? v cmos 3/5 v (type : l, n, o) high voltage range v ih 0.65 v dd ? v dd v low voltage range v il v ss ? 0.25 v dd v cmos 3 v (type : p, w) high voltage range v ih 0.65 v dd ? v dd v low voltage range v il v ss ? 0.25 v dd v input capaci- tance c in ?? 16 pf input leakage current i il - 1 ?+ 1 m at a = 25 c pull up resistor r up1 r up2 ? 50 10 ? k w k w types : e, u type : s
mb91360g series 187 (continued) parameter symbol value unit condition min typ max adc inputs reference voltage input v refh v refl v refl + 3 v ssa ? v dda v refh - 3 v v input voltage range v imax v imin v refl ? ? v refh ? v v input resistance r i ?? 3.6 k w input capacitance c i ?? 30 pf input leakage current i il - 5 ? 5 m a impedance of external output driving the adc input ??? 4.0 k w at sampling time of 1.6 m s dac analog outputs output voltage v out v ssa ? v dda v output impedance r out ? 2.9 ? k w external voltage follower required output capacitance c out ?? 20 pf sound generator output voltage v outhigh v outlow v dd - 0.5 v ss ? v dd v ss + 0.4 v v output current i out 4 ?? ma ppg output voltage v outhigh v outlow v dd - 0.5 v ss ? v dd v ss + 0.4 v v output current i out 4 ?? ma led output voltage v outhigh v outlow v dd - 0.8 ? ? ? v ss + 0.8 v v i outhigh = 14 ma i outlow = 24 ma i 2 c bus interface (open drain output) output voltage v outhigh v outlow ? v ss ? v dd v ss + 0.4 v v open drain output output current i out 3 ?? ma i outlow = 3 ma lock-up time pll1 (4 mhz ? 16 mhz to 64 mhz) ?? 0.1 1 ms esd protection (human body model mil883-b compliant) v surge 2 ?? kv r discharge = 1.5 k w c discharge = 100 pf
mb91360g series 188 4. run mode current/power consumption the power dissipation during normal operation is determined by the total power dissipation of the internal logic p c , the dissipation from analog modules p a and the power dissipation p io of the i/o buffers. among the i/o buffers the dissipation caused by the stepper motor drivers p smc should be taken into special consideration. so the overall power consumption p d will be calculated as a sum of pc + p a + p smc + p io . (1) logic power consumption the following formula can be used to calculate the maximum core current consumption when the pll is used depending on the frequency settings for the internal clocks : i cc = 3.45 [ma/mhz] clkb [mhz] + 2.52 [ma/mhz] clkp[mhz] + 0.72 [ma/mhz] clkt [mhz] + 35.5 ma. if clock modulation is used the following value must be added to this result : 0.24 [ma/mhz] clkb [mhz]. this results in the following values (higher clock settings are not allowed) : in addition to this power consumption of the mcu core logic the following contributions to the overall power con- sumption have to be considered : (2) analog power consumption to calculate the analog power consumption p a , the current contributions of the active modules have to be multi- plied by the maximum analog supply voltage of 5.1 v-or by the maximum digital supply voltage as in case of the power down reset. clock frequencies [mhz] maximum core current consumption [ma] logic power consumption p c at 5.25 v [mw] remarks clkb clkp clkt 64 16 16 308 1.70 no clock modulation possible 48 24 24 290 1.52 48 16 16 264 1.40 32 32 32 257 1.35 32 16 16 205 1.08 24 24 24 202 1.06 24 12 12 163 0.86 16 16 16 146 0.77 2 2 2 40 0.21 no pll, no clock modulation 0.125 0.125 0.125 30 0.16 no pll, no clock modulation module typical current consumption maximum current consumption remarks dac 1 ma / channel current at avcc adc 3 ma 7 ma current at avcc 1.6 ma 2.6 ma current at avrh power down reset 0.26 ma 0.5 ma current at vdd alarm comparator 0.31 ma 0.5 ma current at avcc zero point detection 0.13 ma 0.25 ma current at avcc
mb91360g series 189 (3) i/o and smc power consumption smc drivers : the average current consumption per smc channel is 38.2 ma, for four channels this results in 152.8 ma. at 2 0.5 v this results in 153 mw power consumption p smc for four channels of stepper motor drivers. other i/o buffers : the power dissipation (p io ) (at 5.25 v) of the i/o buffers is represented as the sum of the dynamic power dissipation (p ac ) and the static power consumption (p dc ) . p io = p ac 1.1 + p dc the following table lists values for the calculation of p ac5v and p ac3v : p ac = p ib in f operating rate + p ob on f operating rate p dc is the caused by off chip loads which are drawing static currents. p dc = vo io dc n buffer type power consumption p ib /p ob @ 5v to calculate p ac5v power consumption p ib /p ob @ 3.3v to calculate p ac3v unit normal input 12.4 12.4 m w/mhz (c l in pf) bidirectional input 4 ma bidirectional output 194 + 25 c l 85.5 + 11 c l 4 ma output 8 ma bidirectional output 353 + 25 c l 154 + 11 c l 8 ma output p ib : power consumption of input buffers and bidirectional inputs p ob : power consumption of output buffers and bidirectional outputs in : total number of input buffers and bidirectional buffer inputs on : total number of output buffers and bidirectional buffer outputs f : system frequency operating rate : 1.0 if all buffers are switched simultaneously at system frequency vo : output voltage drop - usually 0.4 v io : output current - usually 4 ma dc n : number of output buffers and bidirectional buffers driving off chip loads causing static currents.
mb91360g series 190 5. clock settings note : f362ga : if the maximum frequency of 64 mhz is set for clkb and an odd division factor for clkt (3, 5, 7, 9, 11, 13, 15) has been selected, then the option to create an asymmetrical clkt must be used (set bit 14 of the f362md register to 1) . clock domain clock name max frequency setting remark core clkb 64 mhz under normal operating conditions 32 mhz for supply voltage between 4.25 and 3.5 v resource bus clkp 32 mhz ext. bus clkt 32 mhz clock for can canclk 32 mhz
mb91360g series 191 6. converter characteristics ? a/d converter ? d/a converter parameter symbol value unit remark min typ max resolution ?? ? 10 bit conversion error ?? ? 5.0 lsb overall error non-linearity ?? ? 2.5 lsb differential non-linearity ?? ? 1.9 lsb zero reading voltage v 0t avrl - 3.5 avrl + 0.5 avrl + 4.5 lsb full scale reading voltage v fst avrh - 5.5 avrh - 1.5 avrh + 2.5 lsb input current ia@v dda ? 3.0 7.0 ma reference voltage current ir ? 1.6 2.6 ma conversion time ? 178 cycles clkp ? 1 ms ripple of supply voltage ?? ? 5.0 mv parameter symbol value unit remark min typ max resolution ?? ? 10 bit differential linearity error ?- 0.9 ?+ 0.9 lsb
mb91360g series 192 7. a/d converter glossary ? resolution the smallest change in analog voltage detected by a/d converter. ? linearity error a deviation of actual conversion characteristic from a line connecting the zero-traction point (between 00 0000 0000 ? 00 0000 0001) to the full-scale transition point (between 11 1111 1110 ? 11 1111 1111) . ? differential linearity error a deviation of a step voltage for changing the lsb of output code from ideal input voltage. ? total e rror a difference between actual value and theoretical value. the overall error includes zero-transition error, full- scale transition error and linearity error. (continued) 3ff 3fe 3fd 004 003 002 001 avrl avrh 1.5 lsb' 0.5 lsb' {1 lsb' (n - 1) + 0.5 lsb'} digital output analog input actual conversion characteristic actual conversion ideal characteristic v nt (measured value) total error of digital output n = v nt - {1 lsb (n - 1) + 0.5 lsb} 1 lsb [lsb] v ot (ideal value) = avrl + 0.5 lsb [v] v fst (ideal value) = avrh - 1.5 lsb [v] v nt : a voltage for causing transition of digital output from (n - 1) to n total error
mb91360g series 193 (continued) 3ff 3fe 3fd 004 003 002 001 avrl avrh {1 lsb (n - 1) + v ot } v nt (measured value) v ot (measured value) digital output actual conversion characteristic ideal characteristic analog input actual conversion characteristic v fst (measured value) n - 1 avrl avrh n - 2 n n + 1 actual conversion characteristic actual conversion characteristic ideal characteristic v nt (measured value) v (n + 1)t (measured value) digital output analog input linearity error of digital output n = v nt - {1 lsb (n - 1) + v ot } 1 lsb [lsb] differential linearity error of digital output n = v ( n + 1 ) t - v nt 1 lsb - 1 [lsb] 1 lsb = v fst - v ot 1022 [v] 1 lsb (ideal value) = avrh - avrl 1023 [v] v ot : a voltage for causing transition of digital output from (000) h to (001) h v fst : a voltage for causing transition of digital output from (3fe) h to (3ff) h v nt : a voltage for causing transition of digital output from (n - 1) h to n linearity error differential linearity error
mb91360g series 194 8. notes on using a/d converter output impedance of external circuit of analog input under following conditions; output impedance of external circuit < 4 k w . if output impedance of external circuit is too high, analog voltage sampling time may be too short for accurate sampling. ? error as the absolute value of avrh decreases, relative error increases. r o r on : 3.6 k w analog input pin comparator c 0 c 0 : 30 pf ? analog input equivalent circuit
mb91360g series 195 9. the time for power supply 10. flash memory erase and programming performance * : t a = + 85 c, v dd = 5.0 v 11. ac characteristics measurement conditions load conditions parameter symbol value unit min typ max power supply raising slope d v/ d t ?? 0.05 v/ m s power supply raising slope t r 80 ??m s parameter condition value unit remarks min typ max sector erase time t a = + 25 c, v dd = 5.0 v ? 115*s excludes 00h programming prior erasure chip erase time ? 14 ? s excludes 00h programming prior erasure half word (16-bit) programming time ? 16 3,600* m s excludes system-level overhead erase/program cycle ? 10,000 ?? cycle data retention time ? 100 k ?? h parameter symbol value unit conditions h level input voltage v ih according to i/o spec v v dd = 4.25 to 5.25 v, t a = - 40 to + 85 c l level input voltage v il v h level output voltage v oh 0.5 v dd v l level output voltage v ol 0.5 v dd v h level input voltage v ih 3.0 v v dd = 3.0 to 3.6 v, t a = - 40 to + 85 c l level input voltage v il 0v h level output voltage v oh 0.5 v dd v l level output voltage v ol 0.5 v dd v v dd 4.2 v 0.2 v d t d v c = 50 pf output pin
mb91360g series 196 external bus clock (v dd = 4.25 v to 5.25 v, t a = - 40 c to + 85 c) note : this is only valid for operation without clock modulator the values for t chcl and t clch are heavily dependent on the load connected to the clk pin. the following diagrams show this dependency for the worst case situation. the first diagram shows the situation for even division ratios between clkb and clkt, the second diagram shows this for odd division ratios between clkb and clkt (asymclkt bit is not set) . it has to note that when the combination of clk frequency and load at clk pin is such that rise or fall times are longer than t cyc / 2 the duty ratio can get worse. signal symbol pin name value unit min max clk cycle t cyc clk t cpt ? ns clk rise ? clk fall t chcl clk t cyc / 2 - 10 t cyc / 2 + 10 ns clk fall ? clk rise t clch clk t cyc / 2 - 10 t cyc / 2 + 10 ns clk t cyc v oh v oh v ol t chcl t clch
mb91360g series 197 even clkb/clkt division ratios : odd clkb/clkt division ratios : 14,0 12,0 10,0 8,0 6,0 4,0 2,0 0,0 0 204060 pf ns 80 100 120 5 v 3.3 v deviation of t chcl from t cyc / 2 versus load 14,0 12,0 10,0 8,0 6,0 4,0 2,0 0,0 0 204060 pf ns 80 100 120 5 v 3.3 v deviation of t chcl from t cyc / 2 versus load
mb91360g series 198 external bus interface (v dd = 4.25 v to 5.25 v, t a = - 40 c to + 85 c) signal symbol pin name value unit min max cs6x to cs0x delay time t chcsl clk cs6x to cs0x ? 15 ns cs6x to cs0x delay time t chcsh ? 15 ns address delay time t chav clk a20 to a0 ? 20 ns data delay time t chdv clk d31 to d0 ? 16 ns rdx delay time t clrl clk rdx ? 15 ns rdx delay time t clrh ? 15 ns wr3x to wr0x delay time t clwl clk wr3x to wr0x ? 15 ns wr3x to wr0x delay time t clwh ? 15 ns effective address t effect data input time t avdv a20 to a0 d31 to d0 ? 3 / 2 t cyc - 30 ns rdx (fall) ? effect data input time t rldv rdx d31 to d0 ? t cyc - 20 ns data set up ? rdx (rise) time t dsrh 25 ? ns rdx (rise) ? data hold time t rhdx 0 ? ns as delay time t chasl as ? 15 ns as delay time t chash as ? 15 ns
mb91360g series 199 v oh v oh clk as v ol v ol v oh v oh v ol v ol v oh v ol t clrl v ol t clwl v ol t chdv v ol v oh t clrh v oh v oh v ol v oh v ol t rhdx v oh t chcsh v oh cs0x - cs6x a23 - a00 rdx d31 - d00 wr3x - wr0x d31 - d00 t cyc t chcsl t chasl t rldv t avdv t chash t clwh t chav t dsrh
mb91360g series 200 rdy (v dd = 4.25 v to 5.25 v, t a = - 40 c to + 85 c) signal symbol pin name value unit min max rdy setup t rdys clk rdy 16 ? ns rdy hold t rdyh clk rdy 0 ? ns clk v oh v oh v ol v ol v il v ih v ih v il t rdyh t rdyh rdy case 1 rdy case 2 t cyc t rdys t rdys
mb91360g series 201 bgrntx (v dd = 4.25 v to 5.25 v, t a = - 40 c to + 85 c) signal symbol pin name value unit min max bgrntx t chbgl clk bgrntx ? 10 ns bgrntx t chbgh ? 10 ns bus access enabled bgrntx falling t xhal bgrntx tcyc - 15 tcyc + 15 ns bus access disabled bgrntx rising t hahv tcyc - 15 tcyc + 15 ns clk v oh t chbgl v oh v oh v oh t chbgh brq bgrntx other ports t cyc t hahv t xhal high-z
mb91360g series 202 dma (v dd = 4.25 v to 5.25 v, t a = - 40 c to + 85 c) * : dstp and deop share a pin. the pin is possible to change dstp and deop functions using a port function register. signal symbol pin name value unit min max dreq t drwh dreq0 5t cyc ? ns dstp t dswh dstp0* 5t cyc ? ns dack t cldl clk dack0 ? 20 ns t cldh ? 20 deop t clel clk deop0 ? 20 ns t cleh ? 20 clk dstp0 dreq0 dack0 deop0 t cyc t dswh t drwh t cldl t cldh t clel t cleh
mb91360g series 203 n package thermal resistance information n ordering information package thermal resistance [ c/w] theta-ja theta-jc 0 m/s 1 m/s 3 m/s fpt-208p-m04 16 13 11 2.5 pga-401c-a02 16 8.5 5.5 ? fpt-160p-m15 16 13 11 2.5 part number package remarks mb91fv360gacr 401-pin ceramic pga (pga-401c-a02) mb91f362gapfvs 208-pin plastic qfp (fpt-208p-m04) mb91f369gapqs1 160-pin plastic qfp (fpt-160p-m15)
mb91360g series 204 n package dimensions (continued) 401-pin ceramic pga (pga-401c-a02) 208-pin plastic qfp (fpt-208p-m04) note : pins width and pins thickness include plating thickness. 48.26 ?0.55 (1.900 ?.022) sq index area 1994 fujitsu limited r401002sc-2-2 2.54 (.100) typ 0.40 ?0.10 (.016 ?.004) dia 45.72 (1.800) ref 1.20 ?0.25 (.047 ?.010) 5.27 (.207) max 3.40 ?0.40 (.134 ?.016) 1.00 (.039) dia typ (4 plcs) extra index pin 1.02 (.040) c typ (4 plcs) c dimensions in mm (inches) c 2000 fujitsu limited f208020s-c-2-3 .148 ?012 +.008 ?.30 +0.20 3.75 details of "a" part 0.50?.20 (.020?008) 0.60?.15 (.024?006) 0.25(.010) (stand off) 0.40 +0.10 ?.15 +.004 ?006 .016 0?8 1 lead no. 52 53 104 105 156 157 208 "a" 0.08(.003) 0.50(.020) 0.22?.05 (.009?002) 0.08(.003) m 28.00?.10(1.102?004)sq 30.60?.20(1.205?008)sq .007 ?003 +.001 ?.08 +0.03 0.17 index (mounting height) dimensions in mm (inches)
mb91360g series 205 (continued) 160-pin plastic qfp (fpt-160p-m15) note : pins width and pins thickness include plating thickness. c 2001 fujitsu limited f160037s-c-2-2 m 0.13(.005) 28.00?.20(1.102?008)sq 32.00?.40(1.260?016)sq 0.65(.026) 0.10(.004) "a" (mounting height) details of "a" part index 1 40 121 160 120 81 ?.07 +0.08 0.32 .013 +.0031 ?0028 ?.03 +0.05 0.17 .007 +.002 ?001 0~8 ?.20 +0.35 3.75 .148 +.014 ?008 0.25(.010) (stand off) ?.15 +0.10 0.40 .016 +.004 ?006 0.80?.20 (.031?008) 0.88?.15 (.035?006) dimensions in mm (inches)
mb91360g series fujitsu limited all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. the products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). please note that fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan. f 0201 ? fujitsu limited printed in japan

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